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m pd17933, 17934 mos integrated circuit document no. u11947ej2v0ds00 (2nd edition) date published july 1998 n cp(k) printed in japan the m pd17933 and 17934 are 4-bit single-chip cmos microcontrollers with hardware for digital tuning systems (dtss). these microcontrollers integrate a prescaler that operates at a voltage as low as 1.05 v and up to 220 mhz, a pll frequency synthesizer, an intermediate frequency (if) counter, and an lcd controller/driver on a single chip. therefore, a high-performance digital tuning system for a portable set can be organized with a single chip. features ? program memory (rom) ? peripheral hardware m pd17933 : 12k bytes (6144 16 bits) general-purpose i/o ports, lcd controller/driver, m pd17934 : 16k bytes (8192 16 bits) serial interface, a/d converter, beep output, ? general-purpose data memory (ram) ) frequency counter 448 4 bits ? interrupt ? instruction execution time external: 1 source 53.3 m s (with 75-khz crystal resonator) internal : 3 sources ? pll frequency synthesizer ? reset by reset pin dual modulus prescaler (220 mhz max.), ? low power consumption programmable divider, phase comparator, ? supply voltage: v dd = 1.05 to 1.8 v charge pump ordering information part number package m pd17933gk- -be9 80-pin plastic tqfp (12 12 mm, 0.5 mm pitch) m pd17934gk- -be9 80-pin plastic tqfp (12 12 mm, 0.5 mm pitch) remark indicates rom code suffix. unless otherwise specified, the m pd17934 is explained as the representative model in this document. 4-bit single-chip microcontrollers with digital tuning system hardware the information in this document is subject to change without notice. 1997 data sheet the mark shows major revised points.
m pd17933, 17934 2 frequency measurement functional outline part number m pd17933 m pd17934 program memory (rom) 12k bytes (6144 x 16 bits) 16k bytes (8192 x 16 bits) general-purpose data memory (ram) 448 4 bits instruction execution time 53.3 m s (with 75-mhz crystal oscillator) general-purpose port ? i/o port : 20 pins ? input port : 11 pins (of which 3 are muxed with lcd segment pins) ? output port : 6 pins stack level ? address stack : 15 levels (stack can be manipulated) ? interrupt stack : 4 levels (stack can be manipulated) vector interrupt ? external : 1 source (int) (maskable interrupt) ? internal : 3 sources (basic timer 0, 8-bit timer, serial interface) timer 3 channels ? basic timer 0 (125 ms) ? basic timer 1 (8 ms, 32 ms) ? 8-bit timer (with event counter) a/d converter 8-bits resolution 3 channels lcd controller/driver ? 20 segments, 4 commons ? 1/4 duty, 1/2 bias, frame frequency: 62.5 hz, drive voltage v lcd1 =3.0 v typ. ? muxed segment pins: 3 (each can be used as general-purpose input port pin.) serial interface 1 channel (3-wire/2-wire modes selectable) pll frequency division mode ? direct division mode (vcol pin) synthesizer ? pulse swallow mode (vcol pin/vcoh pin) reference frequency 6 types selectable (1, 3, 5, 6.25, 12.5, 25 khz) charge pump error out output: 2 pins (eo0 and eo1 pins) phase comparator unlock detectable by program intermediate frequency (if) ? amifc pin: 400 to 500 khz counter ? fmifc pin: 10 to 11 mhz beep output 1 pin (1.5 khz, 3 khz) reset ? reset by reset pin ? watchdog timer reset can be set only once on power application: 4096 or 8192 instructions selectable ? stack pointger overflow/underflow reset can be set only once on power application: interrupt stack and address stack selectable supply voltage v dd = 1.05 to 1.8 v package 80-pin plastic tqfp (12 12 mm, 0.5 mm pitch) 37 pins 2 types
3 m pd17933, 17934 pin configuration (top view) 80-pin plastic tqfp (12 12 mm, 0.5 mm pitch) m pd17933gk- -be9 m pd17934gk- -be9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 p1c0/tm0 p1c1/tm1 p1c2/amifc p1c3/fmifc/amifc v dd 1 nc eo0 eo1 vcol vcoh gnd test reset p2b0 p2b1 p2b2 p2b3 p0a0 p0a1 p1a0 p1a1 p1a2 p1a3 p1d0 p1d1 p1d2 p1d3 p0b0/sck p0b1/si1/so2 p0b2/so1 p0b3/beep v dd 0 cap lcd 0 cap lcd 1 reg lcd 0 reg lcd 1 cap lcd 2 cap lcd 3 reg lcd 2 com0 v dd 2 gnd p0d3/ad2 p0d2/ad1 p0d1/ad0 p0d0 p2c3 p2c2 p2c1 p2c0 x in x out int p0c3 p0c2 p0c1 p0c0 p2a2/lcd19 p2a1/lcd18 p2a0/lcd17 lcd16 lcd15 lcd14 lcd13 lcd12 lcd11 lcd10 lcd9 lcd8 lcd7 lcd6 lcd5 lcd4 lcd3 lcd2 lcd1 lcd0 com3 com2 com1 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
m pd17933, 17934 4 pin name ad0-ad2 : a/d converter inputs amifc : intermediate frequency counter input for am beep : beep output cap lcd 0-cap lcd 3 : capacitor connection for lcd drive voltage com0-com3 : lcd common output eo0, eo1 : error output fmifc : intermediate frequency counter input for fm gnd : ground int : external interrupt input lcd0-lcd19 : lcd segment outputs nc : no connection p0a0, p0a1 : port 0a p0b0-p0b3 : port 0b p0c0-p0c3 : port 0c p0d0-p0d3 : port 0d p1a0-p1a3 : port 1a p1c0-p1c3 : port 1c p1d0-p1d3 : port 1d p2a0-p2a2 : port 2a p2b0-p2b3 : port 2b p2c0-p2c3 : port 2c reg lcd 0-reg lcd 2: regulator output for lcd drive reset : reset input sck : 3-wire serial clock i/o si1 : 3-wire serial data input so1, so2 : 3-wire serial data outputs test : test input tm0, tm1 : timer event inputs vcoh, vcol : local oscillation inputs for pll v dd 0-v dd 2 : power supply x in , x out : crystal resonator connection
5 m pd17933, 17934 block diagram port 2 4 4 4 3 4 4 4 4 4 p0a0, p0a1 p0b0-p0b3 p0c0-p0c3 p0d0-p0d3 p1a0-p1a3 p1c0-p1c3 p1d0-p1d3 p2a0-p2a2 p2b0-p2b3 p2c0-p2c3 voltage doubler a/d converter lcd controller/ driver reg lcd 0 reg lcd 2 cap lcd 0 pll eo0 eo1 vcol vcoh gnd serial interface com0 com3 lcd0 lcd16 lcd17/p2a0 lcd19/p2a2 ad0/p0d1 ad1/p0d2 ad2/p0d3 osc x in x out cpu peripheral tm0/p1c0 tm1/p1c1 interrupt controller 8-bit timer basic timer0 basic timer1 pll voltage regulator v dd 0-v dd 2 reset reset fmifc/amifc/p1c3 amifc/p1c2 frequency counter int beep beep/p0b3 ram 448 4 bits rom pd17933 : 6144 16 bits pd17934 : 8192 16 bits system reg. alu instruction decoder program counter stack 4 13 bits sck/p0b0 si1/so2/p0b1 so1/p0b2 m m cap lcd 3
m pd17933, 17934 6 contents 1. pin functions ............................................................................................................................ 11 1.1 pin function list ................................................................................................................ 11 1.2 equivalent circuits of pins ............................................................................................... 14 1.3 recommended connections of unused pins ................................................................ 18 1.4 cautions on using test pin ............................................................................................ 19 2. program memory (rom) ........................................................................................................ 20 2.1 outline of program memory ............................................................................................. 20 2.2 program memory ................................................................................................................ 21 2.3 program counter ............................................................................................................... 22 2.4 flow of program ................................................................................................................. 22 2.5 cautions on using program memory .............................................................................. 25 3. address stack (ask) .............................................................................................................. 26 3.1 outline of address stack .................................................................................................. 26 3.2 address stack register (asr) ......................................................................................... 26 3.3 stack pointer (sp) .............................................................................................................. 28 3.4 operation of address stack ............................................................................................. 29 3.5 cautions on using address stack .................................................................................. 30 4. data memory (ram) ................................................................................................................. 31 4.1 outline of data memory .................................................................................................... 31 4.2 configuration and function of data memory ................................................................ 33 4.3 data memory addressing ................................................................................................. 35 4.4 cautions on using data memory ..................................................................................... 36 5. system registers (sysreg) ................................................................................................ 37 5.1 outline of system registers ............................................................................................ 37 5.2 system register list ......................................................................................................... 38 5.3 address register (ar) ...................................................................................................... 39 5.4 window register (wr) ...................................................................................................... 41 5.5 bank register (bank) ....................................................................................................... 42 5.6 index register (ix) and data memory row address pointer (mp: memory pointer) ...................................................................................................... 43 5.7 general register pointer (rp) .......................................................................................... 45 5.8 program status word (psword) .................................................................................... 47 6. general register (gr) .......................................................................................................... 49 6.1 outline of general register .............................................................................................. 49 6.2 general register ................................................................................................................ 49 6.3 generating address of general register by each instruction ................................... 50 6.4 cautions on using general register .............................................................................. 50
7 m pd17933, 17934 7. alu (arithmetic logic unit) block .......................................................................................... 51 7.1 outline of alu block ....................................................................................................... 51 7.2 configuration and function of each block ................................................................... 52 7.3 alu processing instruction list ..................................................................................... 52 7.4 cautions on using alu .................................................................................................... 56 8. register file (rf) and control registers ................................................................. 57 8.1 outline of register file ..................................................................................................... 57 8.2 configuration and function of register file ................................................................. 58 8.3 control registers and input/output selection registers ............................................ 59 8.4 lcd segment registers .................................................................................................... 69 8.5 autions on using control register ................................................................................. 69 9. data buffer (dbf) ................................................................................................................... 70 9.1 outline of data buffer ....................................................................................................... 70 9.2 data buffer .......................................................................................................................... 71 9.3 relationships between peripheral hardware and data buffer .................................... 72 9.4 cautions on using data buffer ........................................................................................ 76 10. data buffer stack ................................................................................................................. 77 10.1 outline of data buffer stack ............................................................................................ 77 10.2 data buffer stack register ............................................................................................... 77 10.3 data buffer stack pointer ................................................................................................. 79 10.4 operation of data buffer stack ........................................................................................ 80 10.5 using data buffer stack ................................................................................................... 81 10.6 cautions on using data buffer stack ............................................................................. 81 11. general-purpose port ........................................................................................................ 82 11.1 outline of general-purpose port ..................................................................................... 82 11.2 general-purpose i/o port (p0b, p1a, p1d, p2b, p2c) ................................................. 84 11.3 general-purpose input port (p0d, p1c, p2a) ................................................................ 93 11.4 general-purpose output port (p0a, p0c) ...................................................................... 96 12. interrupt ............................................................................................................................... .... 98 12.1 outline of interrupt block ................................................................................................. 98 12.2 interrupt control block ..................................................................................................... 100 12.3 interrupt stack register .................................................................................................... 106 12.4 stack pointer, address stack registers, and program counter ................................ 110 12.5 interrupt enable flip-flop (inte) ..................................................................................... 110 12.6 accepting interrupt ............................................................................................................ 111 12.7 operations after interrupt has been accepted ............................................................. 116 12.8 returning from interrupt routine .................................................................................... 116 12.9 external interrupts (int pin) ............................................................................................. 117 12.10 internal interrupts .............................................................................................................. 119
m pd17933, 17934 8 13. timers ............................................................................................................................... ............ 120 13.1 outline of timers ............................................................................................................... 120 13.2 basic timer 0 ...................................................................................................................... 121 13.3 basic timer 1 ...................................................................................................................... 125 13.4 timer 0 ............................................................................................................................... .. 131 14. a/d converter .......................................................................................................................... 138 14.1 outline of a/d converter .................................................................................................. 138 14.2 input selection block ........................................................................................................ 139 14.3 compare voltage generation and compare blocks ..................................................... 141 14.4 comparison timing chart ................................................................................................ 143 14.5 using a/d converter .......................................................................................................... 144 14.6 cautions on using a/d converter ................................................................................... 148 14.7 status at reset ................................................................................................................... 148 15. serial interface ..................................................................................................................... 149 15.1 general ............................................................................................................................... . 149 15.2 clock input/output control block and data input/output control block ................. 150 15.3 clock control block .......................................................................................................... 153 15.4 clock counter ..................................................................................................................... 153 15.5 presettable shift register ................................................................................................. 154 15.6 wait control block ............................................................................................................. 154 15.7 serial interface operation ................................................................................................. 155 15.8 notes on setting and reading data ................................................................................ 159 15.9 operation mode and operational outline of each blocks ........................................... 160 15.10 status on reset .................................................................................................................. 162 16. pll frequency synthesizer ............................................................................................... 163 16.1 outline of pll frequency synthesizer ........................................................................... 163 16.2 input selection block and programmable divider ........................................................ 164 16.3 reference frequency generator ..................................................................................... 168 16.4 phase comparator (f-det), charge pump, and unlock ff ......................................... 170 16.5 pll disabled status .......................................................................................................... 174 16.6 using pll frequency synthesizer .................................................................................. 175 16.7 status at reset ................................................................................................................... 179 17. intermediate frequency (if) counter ........................................................................... 180 17.1 outline of frequency counter ......................................................................................... 180 17.2 if counter input selection block and gate time control block ................................ 181 17.3 start/stop control block and if counter ....................................................................... 183 17.4 using if counter ................................................................................................................ 189 17.5 status at reset ................................................................................................................... 191 18. beep ............................................................................................................................... ................ 192 18.1 outlines of beep ............................................................................................................... 192 18.2 output wave form of beep ............................................................................................. 194 18.3 status at reset ................................................................................................................... 195
9 m pd17933, 17934 19. lcd controller/driver ........................................................................................................ 196 19.1 outline of lcd controller/driver ..................................................................................... 196 19.2 lcd drive voltage generation block .............................................................................. 197 19.3 lcd segment register ...................................................................................................... 198 19.4 segment signal/general-purpose input port select block ......................................... 200 19.5 common signal output and segment signal output timing control blocks .......... 202 19.6 common signal and segment signal output waves ................................................... 203 19.7 using lcd controller/driver ............................................................................................ 205 19.8 status at reset ................................................................................................................... 207 20. standby ............................................................................................................................... ........ 208 20.1 outline of standby function ............................................................................................ 208 20.2 halt function ...................................................................................................................... 209 20.3 clock stop function .......................................................................................................... 215 20.4 device operation in halt and clock stop status .......................................................... 217 20.5 cautions on processing of each pin in halt and clock stop status ......................... 217 21. reset ............................................................................................................................... ............. 220 21.1 outline of reset ................................................................................................................. 220 21.2 reset by reset pin .......................................................................................................... 221 21.3 wdt&sp reset ................................................................................................................... 222 22. instruction set ....................................................................................................................... 228 22.1 outline of instruction set ................................................................................................. 228 22.2 legend ............................................................................................................................... .. 229 22.3 instruction list ................................................................................................................... 230 22.4 assembler (ra17k) embedded macro instruction ....................................................... 232 23. reserved symbols ................................................................................................................. 233 23.1 data buffer (dbf) ............................................................................................................... 233 23.2 system registers (sysreg) ............................................................................................ 233 23.3 lcd segment register ...................................................................................................... 234 23.4 port register ....................................................................................................................... 235 23.5 register file (control register) ....................................................................................... 236 23.6 peripheral hardware register .......................................................................................... 238 23.7 others ............................................................................................................................... ... 238 24. electrical characteristics ............................................................................................ 239 25. package drawing .................................................................................................................. 243 26. recommended soldering conditions ........................................................................... 244 appendix a. cautions on connecting crystal resonator ...................................... 245 appendix b. development tools ........................................................................................... 246
m pd17933, 17934 10 memo
11 m pd17933, 17934 1. pin functions 1.1 pin function list pin no. symbol function output form 1 pic0/tm0 port 1c, timer event input pins, if counter (for frequency count) input pin for 2 p1c1/tm1 the am/fm. 3 p1c2/amifc ? pic0 through p1c3 4 p1c3/fmifc/ 4-bit input port amifc ? tm0 and tm1 timer event input pins ? amifc if counter input pin for am ? fmifc if counter input pin for fm at reset on clock stop reset by reset pin wdt&sp reset input (p1c0-p1c3) input (p1c0-p1c3) input (p1c0-p1c3) 80 v dd 2 power supply pins. supply the same voltage to these pins. C 5v dd 1v dd 2: supplies power to the comparator and peripherals of the a/d converter, 32 v dd 0 and to the if counter. v dd 1: supplies power to the pll. v dd 0: supplies power to all the internal circuits except the above. 6 nc no connection C 7 eo0 output from the charge pump of the pll frequency synthesizer. cmos 8 eo1 these pins output the result of comparing the phases of the divided frequency 3-state of local oscillation with the reference frequency. at reset on clock stop reset by reset pin wdt&sp reset high-impedance output high-impedance output high-impedance output 9 vcol input of the local oscillation (vco) frequency of the pll. C 10 vcoh ? vcol ? active when hf or mf mode selected by program; otherwise; pulled down. ? vcoh ? active when vhf mode selected by program; otherwise, pulled down. because these input pins are connected to an internal ac amplifier, cut the dc component of the input signal with a capacitor. 11 gnd ground C 79 12 test test input pin. be sure to connect this pin directly to gnd. C 13 reset reset input C
m pd17933, 17934 12 pin no. symbol function output form 14 p2b0 these pins form a 4-bit i/o port which can be set in input or output mode in cmos | | 1-bit units. push-pull 17 p2b3 at reset on clock stop reset by reset pin wdt&sp reset input input retained 18 p0a0 these pins form a 2-bit output port. n-ch open- 19 p0a1 at reset on clock stop drain reset by reset pin wdt&sp reset output low level output low level retained 20 p1a0 these pins form a 4-bit i/o port which can be set in input or output mode in n-ch open- | | 1-bit units. drain 23 p1a3 at reset on clock stop reset by reset pin wdt&sp reset input input retained 24 p1d0 these pins form a 4-bit i/o port which can be set in input or output mode in n-ch open- | | 1-bit units. drain 27 p1d3 at reset on clock stop reset by reset pin wdt&sp reset input input retained 28 p0b0/sck port p0b, the i/o pins of the serial interface and beep output pin. cmos | p0b1/si1/so2 ? p0b3 through p0b0 push-pull 31 p0b2/so1 ? 4-bit i/o port p0b3/beep ? can be set in input or output mode in 1-bit units. ? beep ? beep output ? so1, so2, si1 serial data output pins and serial data input pin when the 3-wire or 2-wire serial i/o mode of serial interface 1 is selected. ? sck ? serial clock i/o at reset on clock stop reset by reset pin wdt&sp reset input (p0b3-p0b0) input (p0b3-p0b0) retained 33 cap lcd 0 these pins can be used to connect capacitors for a double circuit to generate C 34 cap lcd 1 power to drive an lcd. connect 0.33 m f capacitors between cap lcd 0 and 37 cap lcd 2 cap lcd 1 pins and between cap lcd 2 and cap lcd 3 pins. 38 cap lcd 3 35 reg lcd 0 regulator output pins of power supply for lcd drive. C 36 reg lcd 1 connect to gnd with a 0.1 m f capacitor. 39 reg lcd 2
13 m pd17933, 17934 pin no. symbol function output form 40 com0 these pins output the common signals of the lcd controller/driver. cmos | | at reset on clock stop 3-state 43 com3 reset by reset pin wdt&sp reset output low level output low level output low level 44 lcd0 these pins are the segment signal output pins of the lcd controller/driver. cmos | | push-pull 60 lcd16 61 p2a0/lcd17 port 2a input port, the segment signal output pins of the lcd controller/driver. C | p2a1/lcd18 ? p2a0 through p2a2 63 p2a2/lcd19 3-bit input port ? lcd17 through lcd19 lcd segment output at reset on clock stop reset by reset pin wdt&sp reset input (p2a2-p2a0) input (p2a2-p2a0) retained 64 p0c0 4-bit output cmos | | at reset on clock stop push-pull 67 p0c3 reset by reset pin wdt&sp reset output low level output low level retained 68 int edge-detected vector interrupt input. C rising or falling edge is selectable. 69 x out crystal resonator connection pin. C 70 x in 71 p2c0 these pins form a 4-bit i/o port which can be set in the input or output mode cmos | | in 1-bit units. push-pull 74 p2c3 at reset on clock stop reset by reset pin wdt&sp reset input input retained 75 p0d0 port 0d input port, a/d converter input pins and to release the halt C | p0d1/ad0 and stop modes. 78 p0d2/ad1 ? p0d0 through p0d3 p0d3/ad2 4-bit input port ? ad0 through ad2 analog input of a/d converter ? halt and stop mode releasing releases halt or stop mode when a high level is input. at reset on clock stop reset by reset pin wdt&sp reset input with pull-down resistor input with pull-down resistor retained (p0d3-p0d0) (p0d3-p0d0)
m pd17933, 17934 14 1.2 equivalent circuits of pins (1) p0b (p0b3/beep, p0b2/so1, p0b1/si1/so2, p0b0/sck) p2b (p2b3, p2b2, p2b1, p2b0) (i/o) p2c (p2c3, p2c2, p2c1, p2c0) (3) p0a (p0a1, p0a0) (output) (2) p1a (p1a3, p1a2, p1a1, p1a0) (i/o) p1d (p1d3, p1d2, p1d1, p1d0) v dd v dd v dd
15 m pd17933, 17934 (4) p0c (p0c3, p0c2, p0c1, p0c0) (output) (5) p0d (p0d3/ad2, p0d2/ad1, p0d1/ad0, p0d0) p1c (p1c3/fmifc/amifc, p1c2/amifc, p1c1/tm1, pic0/tm0) (input) p2a (p2a2/lcd19, p2a1/lcd18, p2a0/lcd17) (6) int reset (schmitt trigger input) (7) x out (output), x in (input) v dd v dd v dd v dd high on resistance high on resistance x out x in v dd high on resistance ( p0d onl y)
m pd17933, 17934 16 (8) eo1, eo0 (output) (9) com3 through com0 (output) (10)vcoh (input) v lcd1 v lcd0 v dd v dd high on resistance v dd dwn up
17 m pd17933, 17934 (11)vcol (input) v dd high on resistance v dd high on resistance pll disable signal pll disable signal
m pd17933, 17934 18 1.3 recommended connections of unused pins it is recommended to connect the unused pins as follows: table 1-1. recommended connections of unused pins pin name i/o form recommended connection port pins p0d3/ad2-p0d1/ad0,p0d0 input connect each pin to gnd via resistor note 1 . p1c3/fmifc/amifc note 2 p1c2/amifc note 2 p1c1/tm1 set each pin in port mode and connect it to v dd or gnd p1c0/tm0 via resistor. p0a1, p0a0 output set in low-level output mode via software and leave p0c3-p0c0 unconnected. p0b3/beep i/o note 3 set in general-purpose input port mode via software, and p0b2/so1 connect each pin to v dd or gnd via resistor. p0b1/si1/so2 p0b0/sck p1a3-p1a0 p1d3-p1d0 p2a2/lcd19 p2a1/lcd18 p2a0/lcd17 p2b3-p2b0 p2c3-p2c0 eo1 output leave unconnected. eo0 int input connect to gnd via resistor note 1 . nc C leave unconnected. test C directly connect to gnd. vcoh input set to pll disable via software and leave unconnected. vcol notes 1. if these pins are externally pulled up (connected to v dd via resistor) or down (connected to gnd via resistor) with a high resistor, the pins almost go into a high-impedance state, increasing the current consumption (through current) of the port. although the value of the pull-up or pull-down resistor varies depending on the application circuit, it generally is several 10 k w . 2. the circuit of the general-purpose input port is designed not to increase the current consumption even in the high-impedance state. do not set these pins in the amifc and fmifc modes; otherwise, the current consumption will increase. 3. the i/o ports are set in the general-purpose input port mode at reset by the reset pin and reset due to overflow/underflow of the watchdog timer or stack, and on execution of the clock stop instruction. pins other than port pins
19 m pd17933, 17934 1.4 cautions on using test pin when v dd is applied to the test pin, the device is set in the test mode. therefore, be sure to keep the wiring length of this pin as short as possible, and directly connect it to the gnd pin. if the wiring length between the test pin and gnd pin is too long, or if external noise is superimposed on the test pin, generating a potential difference between the test pin and gnd pin, your program may not run normally. gnd test short
m pd17933, 17934 20 2. program memory (rom) 2.1 outline of program memory figure 2-1 outlines the program memory. as shown in this figure, the addresses of the program memory are specified by the program counter. the program memory has the following two major functions. ? to store programs ? to store constant data figure 2-1. outline of program memory instruction constant data program memory program counter address specification
21 m pd17933, 17934 2.2 program memory figure 2-2 shows the configuration of the program memory. as shown in this figure, the program memory consists of: m pd17933: 6144 16 bits (0000h-17ffh) m pd17934: 8192 16 bits (0000h-1fffh) because all instructions are one-word instructions, one instruction can be stored to one address of the program memory. as constant data, the contents of the program memory are read to the data buffer by using a table reference instruction. figure 2-2. configuration of program memory 16 bits h br addr instruction branch address br @ar instruction branch address call @ar instruction subroutine entry address movt dbf, @ar instruction table reference address address h h h h h h h h ( pd17933) reset start address serial interface 1 interrupt vector basic timer 1 interrupt vector timer 0 interrupt vector int pin interrupt vector page 0 page 1 page 2 page 3 call addr instruction subroutine entry address 0 1 2 3 4 f f f f 0 0 0 0 0 f f f f 0 0 0 0 0 7 f 7 f 0 0 0 0 0 0 0 1 1 m ( pd17934) m
m pd17933, 17934 22 2.3 program counter 2.3.1 configuration of program counter figure 2-3 shows the configuration of the program counter. as shown in this figure, the program counter consists of a 13-bit binary counter. bits 11 and 12 of the program counter indicate a page. the program counter specifies an address of the program memory. figure 2-3. configuration of program counter 2.4 flow of program the flow of the program is controlled by the program counter that specifies an address of the program memory. the program flow when each instruction is executed is described below. figure 2-4 shows the value that is set to the program counter when each instruction is executed. table 2-4 shows the vector address when an interrupt is accepted. 2.4.1 branch instruction (1) direct branch (br addr) the branch destination addresses of the direct branch instruction are all the addressess of the program memory. (2) indirect branch (br @ar) the branch destination addresses of the indirect branch instruction are all the addresses of the program memory. the addresses are 0000h through 17ffh in the m pd17933, and 0000h through 1fffh in the m pd17934. refer to 5.3 address register (ar) . pc 0 page pc pc 12 pc 11 pc 10 pc 9 pc 8 pc 7 pc 6 pc 5 pc 4 pc 3 pc 2 pc 1
23 m pd17933, 17934 2.4.2 subroutine (1) direct subroutine call (call addr) the first address of a subroutine that can be called by the direct subroutine instruction is in page 0 (addresses 0000h through 07ffh). (2) indirect subroutine call (call @ar) the first addresses of a subroutine that can be called by the indirect subroutine call instruction are all the addresses of the program memory. the addresses are 0000h through 17ffh in the m pd17933, and 0000h through 1fffh in the m pd17934. refer to 5.3 address register (ar). 2.4.3 table reference the addresses that can be referenced by the table reference instruction (movt dbf, @ar) are all the addresses of the program memory. the addresses are 0000h through 17ffh in the m pd17933, and 0000h through 1fffh in the m pd17934. refer to 5.3 address register (ar) and 9.2.2 table reference instruction (movt, dbf, @ar) .
m pd17933, 17934 24 figure 2-4. value of program counter upon execution of instruction table 2-1. interrupt vector address order internal/external interrupt source vector address 1 external int pin 0004h 2 internal timer 0 0003h 3 internal basic timer 1 0002h 4 internal serial interface 1 0001h contents of program counter (pc) b 12 0 0 1 1 0 0 b 11 0 1 0 1 0 0 b 10 0 b 9 0 b 8 0 b 7 0 b 6 0 b 5 0 b 4 0 b 3 0 b 2 0 b 1 0 b 0 0 program counter instruction br addr call addr br @ar call @ar movt dbf, @ar ret retsk reti other instructions (including skip instruction) when interrupt is accepted watchdog timer reset, reset by reset pin page 0 page 1 page 2 page 3 operand of instruction (addr) operand of instruction (addr) contents of address register contents of address stack register (asr) (return address) specified by stack pointer (sp) vector address of each interrupt increment
25 m pd17933, 17934 2.5 cautions on using program memory (1) m pd17933 the program memory of the m pd17933 is assigned to addresses 0000h through 17ffh. however, addresses that can be specified by the program counter (pc) are 0000h through 1fffh, therefore, be careful on the following points when specifying the program memory addresses. ? write a branch instruction when writing an instruction to address 17ffh. ? do not write anything to addresses 1800h through 1fffh. ? do not branch to addresses 1800h through 1fffh. (2) m pd17934 the program memory of the m pd17934 is assigned to addresses 0000h through 1fffh. be careful on the following points. ? write a branch instruction when writing an instruction to address 1fffh.
m pd17933, 17934 26 3. address stack (ask) 3.1 outline of address stack figure 3-1 outlines the address stack. the address stack consists of a stack pointer and address stack registers. the address of an address stack register is specified by the stack pointer. the address stack saves a return address when a subroutine call instruction is executed or when an interrupt is accepted. the address stack is also used when the table reference instruction is executed. figure 3-1. outline of address stack 3.2 address stack register (asr) figure 3-2 shows the configuration of the address stack register. the address stack register consists of sixteen 13-bit registers asr0 through asr15. actually, however, it consists of fifteen 13-bit registers (asr0 through asr14) because no register is allocated to asr15. the address stack saves a return address when a subroutine is called, when an interrupt is accepted, and when the table reference instruction is executed. stack pointer return address address stack register address specification
27 m pd17933, 17934 figure 3-2. configuration of address stack register b 3 b 2 b 1 b 0 stack pointer (sp) b 3 sp3 b 2 sp2 b 1 sp1 b 0 sp0 b 12 b 11 b 10 b 9 b 8 b 7 b 6 b 5 b 4 bit address stack register (asr) address 0h 1h 2h 3h 4h 5h 6h 7h 8h 9h ah bh ch dh eh fh asr0 asr1 asr2 asr3 asr4 asr5 asr6 asr7 asr8 asr9 asr10 asr11 asr12 asr13 asr14 asr15 (undefined) ? cannot be used bit
m pd17933, 17934 28 3.3 stack pointer (sp) 3.3.1 configuration and function of stack pointer figure 3-3 shows the configuration and functions of the stack pointer. the stack pointer consists of a 4-bit binary counter. it specifies the address of an address stack register. a value can be directly read from or written to the stack pointer by using a register manipulation instruction. figure 3-3. configuration and function of stack pointer retained reset by reset pin wdt&sp reset clock stop name flag symbol b 3 s p 3 b 2 s p 2 b 1 s p 1 b 0 s p 0 address 01h read/write r/w stack pointer (sp) 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 address 0 (asr0) address 1 (asr1) address 2 (asr2) address 3 (asr3) address 4 (asr4) address 5 (asr5) address 6 (asr6) address 7 (asr7) address 8 (asr8) address 9 (asr9) address 10 (asr10) address 11 (asr11) address 12 (asr12) address 13 (asr13) address 14 (asr14) setting prohibited specifies address of address stack register (asr) 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 1 at reset ( ( ( ( reset by reset pin wdt&sp reset clock stop : reset by reset pin : reset by watchdog timer and stack pointer : upon execution of clock stop instruction ( ( ( (
29 m pd17933, 17934 3.4 operation of address stack 3.4.1 subroutine call instruction (call addr, call @ar) and return instruction (ret, retsk) when a subroutine call instruction is executed, the value of the stack pointer is decremented by one, and the return address is stored to an address stack register specified by the stack pointer. when the return instruction is executed, the contents of the address stack register (return address) specified by the stack pointer are restored to the program counter, and the value of the stack pointer is incremented by one. 3.4.2 table reference instruction (movt dbf, @ar) when the table reference instruction is executed, the value of the stack pointer is incremented by one, and the return address is stored to an address stack register specified by the stack pointer. next, the contents of the program memory specified by the address register are read to the data buffer, the contents of the address stack register (return value) specified by the stack pointer are restored to the program counter, and the value of the stack pointer is incremented by one. 3.4.3 when interrupt is accepted and on execution of return instruction (reti) when an interrupt is accepted, the value of the stack pointer is decremented by one, and the return address is stored to an address stack register specified by the stack pointer. when the return instruction is executed, the contents of an address stack register (return value) specified by the stack pointer are restored to the program counter, and the value of the stack pointer is incremented by one. 3.4.4 address stack manipulation instruction (push ar, pop ar) when the push instruction is executed, the value of the stack pointer is decremented by one, and the contents of the address register are transferred to an address stack register specified by the stack pointer. when the pop instruction is executed, the contents of an address stack register specified by the stack pointer are transferred to the address register, and the value of the stack pointer is incremented by one.
m pd17933, 17934 30 3.5 cautions on using address stack 3.5.1 nesting level and operation on overflow the value of address stack register (asr15) is undefined when the value of the stack pointer is 0fh. accordingly, if a subroutine call exceeding 15 levels, or an interrupt is used without manipulating the stack, execution returns to an undefined address. 3.5.2 reset on detection of overflow or underflow of address stack whether the device is reset on detection of overflow or underflow of the address stack can be specified by program. at reset, the program is started from address 0, and some control registers are initialized. this reset function is valid at reset by the reset pin. for details, refer to 21. reset .
31 m pd17933, 17934 4. data memory (ram) 4.1 outline of data memory figure 4-1 outlines the data memory. as shown in the figure, system registers, a data buffer, port registers, lcd segment registers, and control registers are located on the data memory. the data memory stores data, transfers data with the peripheral hardware or ports, and controls the cpu.
m pd17933, 17934 32 figure 4-1. outline of data memory notes 1. lcd segment registers are allocated to addresses 5ch through 6fh of bank14. 2. control registers are allocated to addresses 00h through 6fh of bank15. port input/output select registers are allocated to 60h through 6fh. cautions 1. never write anything to address 31h of bank15 because this address is a test mode area. 2. address 5bh is not provided to bank4 through bank14. peripheral hardware data transfer column address data memory bank0 port registers port registers port registers bank1 bank2 bank3 bank14 note 1 bank15 note 2 system registers ports 0123456789abcdef data transfer 0 1 2 3 4 5 6 7 data buffer row address lcd segment register lcd data transfer peripheral hardware condition setting ......
33 m pd17933, 17934 4.2 configuration and function of data memory figure 4-2 shows the configuration of the data memory. as shown in this figure, the data memory is divided into several banks with each bank made up of a total of 128 nibbles with 7h row addresses and 0fh column addresses. the data memory can be divided into five functional blocks. each block is described in 4.2.1 through 4.2.6 below. the contents of the data memory can be operated on, compared, judged, and transferred in 4-bit units with a single data memory manipulation instruction. table 4-1 lists the data memory manipulation instructions. 4.2.1 system registers (sysreg) the system registers are allocated to addresses 74h through 7fh. because the system registers are allocated to all banks, the same system registers exist at addresses 74h through 7fh of any bank. for details, refer to 5. system register (sysreg) . 4.2.2 data buffer (dbf) the data buffer is allocated to addresses 0ch through 0fh of bank 0. for details, refer to 9. data buffer (dbf) . 4.2.3 port registers the port registers are allocated to addresses 70h through 73h of banks 0 through 2. for details, refer to 11. general-purpose ports . 4.2.4 control registers and port input/output select registers the control registers are allocated to addresses 00h through 6fh of bank 15. of these registers, the port input/output select registers are allocated to addresses 60h through 6fh of bank15. addresses 00h through 3fh of bank15, to which control registers are allocated, also overlap addresses 00h through 3fh of the register file. for details, refer to 8. register file (rf) and control registers . 4.2.5 lcd segment registers the lcd segment registers consists of a total of 20 nibbles at addresses 5ch through 6fh of bank15 of the data memory. for details, refer to 8.4 lcd segment registers and 19. lcd controller/driver. 4.2.6 general-purpose data memory the general-purpose data memory is allocated to the addresses of the data memory excluding those of the system registers, control registers, port registers, port input/output selection registers, and lcd segment register. the general-purpose data memory consists of a total of 448 nibbles of the 112 nibbles each of banks 0 through 3.
m pd17933, 17934 34 figure 4-2. configuration of data memory notes 1. the high-order 2 bits of 70h are fixed to 0. 2. the same system register exists. 3. address 71h of bank1, and the high-order 1 bit and address 73h of bank2 are fixed to 0. cautions 1. never write anything to address 31h of bank15 because this address is a test mode area. 2. address 5bh is not provided to bank4 through bank14. system registers bank0 data memory 0 1 2 3 4 5 6 7 0 bank1 column address 01 0 1 2 3 4 5 6 7 general registers system registers (sysreg) note 2 0 1 2 3 4 5 6 7 port register note 3 system registers (sysreg) note 2 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 system registers (sysreg) note 2 system registers (sysreg) note 2 123456789abcdef bank2 bank14 bank15 23456789ab c def data buffer 0123456789ab c def 0123456789ab c def fixed to 0 column address fixed to 0 0123456789ab c def bank0 column address bank1-bank2 column address bank3 column address bank14 port register note 1 lcd segment register row address row address row address row address row address 0 1 2 3 4 5 6 7 system registers (sysreg) note 2 fixed to 0 0123456789ab c def column address bank15 port input/output selection registers row address unmounted control register fixed to 0
35 m pd17933, 17934 data memory address bank register column address row address bank b 3 b 2 b 1 b 0 b 2 b 1 b 0 b 3 b 2 b 1 b 0 instruction operand table 4-1. data memory manipulation instructions function instruction operation add add addc subtract sub subc logic and or xor compare ske skge sklt skne transfer mov ld st judge skt skf 4.3 data memory addressing figure 4-3 shows address specification of the data memory. an address of the data memory is specified by a bank, row address, and column address. a row address and a column address are directly specified by a data memory manipulation instruction. however, a bank is specified by the contents of a bank register. for the details of the bank register, refer to 5. system register (sysreg) . figure 4-3. address specification of data memory
m pd17933, 17934 36 4.4 cautions on using data memory 4.4.1 at reset by reset pin the contents of the general-purpose data memory are undefined at reset by reset pin. initialize the data memory as necessary. 4.4.2 cautions on data memory not provided if a data memory manipulation instruction that reads the data memory is executed to a data memory address not provided, undefined data is read. nothing is changed even if data is written to such an address.
37 m pd17933, 17934 5. system registers (sysreg) 5.1 outline of system registers figure 5-1 shows the location of the system registers on the data memory and their outline. as shown in the figure, the system registers are allocated to addresses 74h through 7fh of all the banks of the data memory. therefore, identical system registers exist at addresses 74h through 7fh of any bank. because the system registers are located on the data memory, they can be manipulated by all data memory manipulation instructions. seven types of system registers are available depending on function. figure 5-1. location and outline of system registers on data memory column address data memory bank0 bank1 bank2 0123456789abcdef 0 1 2 3 4 5 6 7 bank14 bank15 system register address name function 74h 75h 76h 77h 78h 79h 7ah 7bh 7ch 7dh 7eh 7fh address register (ar) controls program memory address window register (wr) transfers data with register file bank register (bank) specifies bank of data memory data memory row address pointer (mp) index register (ix) modifies address of data memory general register pointer (rp) specifies address of general register program status word (psword) controls operation row address ...... remark address 5bh is not provided to bank4 through bank14. bank3
m pd17933, 17934 38 5.2 system register list figure 5-2 shows the configurations of the system registers. figure 5-2. configuration of system registers address name symbol bit data 74h 75h 76h 77h 78h 79h 7ah 7bh 7ch 7dh 7eh 7fh address register (ar) window register (wr) bank register (bank) data memory row address pointer (mp) index register (ix) general register pointer (rp) program status word (psword) system registers ar3 ar2 ar1 ar0 wr bank ixh mph ixm mpl ixl rph rpl psw b 2 b 1 b 0 b 3 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 m p e b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b c d b 3 b 2 b 1 b 0 c m p c y zi x e (rp) (ix) (mp)
39 m pd17933, 17934 5.3 address register (ar) 5.3.1 configuration of address register figure 5-3 shows the configuration of the address register. as shown in the figure, the address register consists of 16 bits of system register addresses 74h through 77h (ar3 through ar0). figure 5-3. configuration of address register address name symbol bit data 74h ar3 75h ar2 76h ar1 77h ar0 b 3 m s b b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 l s b reset by reset pin wdt&sp reset clock stop ? address register (ar) at reset 0 0 retained 0 0 retained 0 0 retained 0 0 retained reset by reset pin wdt&sp reset clock stop : reset by reset pin : reset by watchdog timer and stack pointer : on execution of clock stop instruction ?
m pd17933, 17934 40 5.3.2 function of address register the address register specifies a program memory address when the table reference instruction (movt dbf, @ar), stack manipulation instruction (push ar, pop ar), indirect branch instruction (br @ar), or indirect subroutine call instruction (call @ar) is executed. a dedicated instruction (inc ar) is available that can increment the contents of the address instruction by one. the following paragraphs (1) through (5) describe the operation of the address register when the respective instructions are executed. (1) table reference instruction (movt dbf, @ar) when the table reference instruction is executed, the constant data (16 bits) of a program memory address specified by the contents of the address register are read to the data buffer. the constant data that can be specified by the address register is stored to address 0000h to 17ffh in the case of the m pd17933, and address 0000h to 1fffh in the case of the m pd17934. (2) stack manipulation instruction (push ar, pop ar) when the push ar instruction is executed, the value of the stack pointer is decremented by one, and the contents of the address register (ar) are transferred to an address stack register specified by the stack pointer whose value has been decremented by one. when the pop ar instruction is executed, the contents of an address stack register specified by the stack pointer are transferred to the address register, and the value of the stack pointer is incremented by one. (3) indirect branch instruction (br @ar) when this instruction is executed, the program branches to a program memory address specified by the contents of the address register. the branch address that can be specified by the address register is 0000h to 17ffh in the case of the m pd17933, and 0000h to 1fffh in the case of the m pd17934. (4) indirect subroutine call instruction (call @ar) the subroutine at a program memory address specified by the contents of the address register can be called. the first address of the subroutine that can be specified by the address register is 0000h to 17ffh in the case of the m pd17933, and 0000h to 1fffh in the case of the m pd17934. (5) address register increment instruction (inc ar) this instruction increments the contents of the address register by one. 5.3.3 address register and data buffer the address register can transfer data as part of the peripheral hardware via the data buffer. for details, refer to 9. data buffer (dbf) . 5.3.4 cautions on using address register because the address register is configured in 16 bits, it can specify an address up to ffffh. however, the program memory exists at addresses 0000h through 17ffh in the case of the m pd17933 and addresses 0000h through 1fffh in the case of the m pd17934. therefore, the maximum value that can be set to the address register of the m pd17933 is address 17ffh. in the case of the m pd17934, it is address 1fffh.
41 m pd17933, 17934 5.4 window register (wr) 5.4.1 configuration of window register figure 5-4 shows the configuration of the window register. as shown in the figure, the window register consists of 4 bits of system register address 78h (wr). figure 5-4. configuration of window register 5.4.2 function of window register the window register is used to transfer data with the register file (rf) to be described later. data transfer between the window register and register file is manipulated by using dedicated instructions peek wr, rf and poke, rf wr (rf: address of register file). the following paragraphs (1) and (2) describe the operation of the window register when these instructions are executed. for further information, also refer to 8. register file (rf) and control registers . (1) peek wr, rf instruction when this instruction is executed, the contents of the register file addressed by rf are transferred to the window register. (2) poke rf, wr instruction when this instruction is executed, the contents of the window register are transferred to the register file addressed by rf. address name symbol bit data clock stop 78h window register (wr) wr undefined retained b 3 m s b b 2 b 1 b 0 l s b reset by reset pin wdt&sp reset at reset ? ?
m pd17933, 17934 42 5.5 bank register (bank) 5.5.1 configuration of bank register figure 5-5 shows the configuration of the bank register. as shown in the figure, the bank register consists of 4 bits of system register address 79h (bank). figure 5-5. configuration of bank register 5.5.2 function of bank register the bank register specifies a bank of the data memory. table 5-1 shows the relationships between the value of the bank register and a bank of the data memory that is specified. because the bank register is one of the system registers, its contents can be rewritten regardless of the bank currently specified. when manipulating a bank register, therefore, the status of the bank at that time is irrelevant. table 5-1. data memory bank specification remark addresses 00h through 5bh are not provided to bank4 through bank14. caution the area to which the data memory is allocated differs depending on the model. for details, refer to figure 4-2 configuration of data memory. address name symbol bit data clock stop 79h bank register (bank) bank 0 0 retained b 3 m s b b 2 b 1 b 0 l s b reset by reset pin wdt&sp reset at reset ? ? bank register (bank) bank of data memory b 3 b 2 b 1 b 0 0 0 0 0 1 1 0 0 0 0 1 1 0 0 1 1 1 1 0 1 0 1 0 1 bank0 bank1 bank2 bank3 bank14 bank15
43 m pd17933, 17934 5.6 index register (ix) and data memory row address pointer (mp: memory pointer) 5.6.1 configuration of index register and data memory row address pointer figure 5-6 shows the configuration of the index register and data memory row address pointer. as shown in the figure, the index register consists of an index register (ix) made up of 11 bits (the low-order 3 bits (ixh) of system register address 7ah, and 7bh and 7ch (ixm, ixl)) and an index enable flag (ixe) at the lowest bit position of 7fh (psw). the data memory row address pointer (memory pointer) consists of a data memory row address pointer (mp) that is made up of 7 bits of the low-order 3 bits of 7ah (mph) and 7bh (mpl), and a data memory row address pointer enable flag (memory pointer enable flag: mpe) at the lowest bit position of 7ah (mph). in other words, the high-order 7 bits of the index register are shared with the data memory row address pointer figure 5-6. configuration of index register and data memory row address pointer address name symbol bit data clock stop 7ah ixh mph 0 0 retained 7bh index register (ix) ixm mpl 0 0 retained 7ch ixl 0 0 retained 7eh 7fh psw memory pointer (mp) b 3 m p e b 2 m s b m s b b 1 b 0 b 3 b 2 b 1 b 0 l s b b 3 b 2 b 1 b 0 l s b b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 i x e 0 0 r reset by reset pin wdt&sp reset ix program status word (psword) mp at reset r: retained ? ? ? ?
m pd17933, 17934 44 5.6.2 functions of index register and data memory row address pointer the index register and data memory row address pointer modify the addresses of the data memory. the following paragraphs (1) and (2) describe their functions. a dedicated instruction (inc ix) that increments the value of the index register by one is available. for the details of address modification, refer to 7. alu (arithmetic logic unit) block . (1) index register (ix) when a data memory manipulation instruction is executed, the data memory address is modified by the contents of the index register. this modification, however, is valid only when the ixe flag is set to 1. to modify the address, the bank, row address, and column address of the data memory are ored with the contents of the index register, and the instruction is executed to a data memory address (called real address) specified by the result of this or operation. all data memory manipulation instructions are subject to address modification by the index register. the following instructions, however, are not subject to address modification by the index register. inc ar rorc r inx ix call addr movt dbf, @ar call @ar push ar ret pop ar retsk peek wr,rf reti poke rf,wr ei get dbf,p di put p, dbf stop s br addr halt h br @ar nop (2) data memory row address pointer (mp) when the general register indirect transfer instruction (mov @r,m or mov m,@r) is executed, the indirect transfer destination address is modified. this modification, however, is valid only when the mpe flag is set to 1. to modify the address, the bank and row address at the indirect transfer destination are replaced by the contents of the data memory row address pointer. instructions other than the general register indirect transfer instruction are not subject to address modification. (3) index register increment instruction (inc ix) this instruction increments the contents of the index register by one. because the index register is configured of 10 bits, its contents are incremented to 000h if the inc ix instruction is executed when the contents of the index register are 3ffh.
45 m pd17933, 17934 5.7 general register pointer (rp) 5.7.1 configuration of general register pointer figure 5-7 shows the configuration of the general register pointer. as shown in the figure, the general register pointer consists of 7 bits including 4 bits of system register address 7dh (rph) and the high-order 3 bits of address 7eh (rpl). figure 5-7. configuration of general register pointer 7dh rph 0 0 retained 7eh rpl 0 0 retained b 3 m s b b 2 b 1 b 0 b 3 b 2 b 1 l s b b 0 b c d general register pointer (rp) address name symbol bit data clock stop reset by reset pin wdt&sp reset at reset ? ? ?
m pd17933, 17934 46 5.7.2 function of general register pointer the general register pointer specifies a general register on the data memory. figure 5-8 shows the addresses of the general registers specified by the general register pointer. as shown in the figure, a bank is specified by the high-order 4 bits (rph: address 7dh) of the general register pointer, and a row address is specified by the low-order 3 bits (rpl: address 7eh). because the valid number of bits of the general register pointer is 7, all the row addresses (0h through 7fh) of all the banks can be specified as general registers. for the details of the operation of the general register, refer to 6. general register (gr) . figure 5-8. address of general register specified by general register pointer remark address 5bh is not provided to bank4 through bank14. 5.7.3 cautions on using general register pointer the lowest bit of address 7eh (rpl) of the general register pointer is allocated as the bcd flag of the program status word. when rewriting rpl, therefore, pay attention to the value of the bcd flag. general register pointer (rp) rph rpl b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 specifies row address of each bank bank bank0 bank15 row address 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 specifies bank 0h 1h 2h 3h 4h 5h 6h 7h l s b b c d m s b ? ? ?
47 m pd17933, 17934 5.8 program status word (psword) 5.8.1 configuration of program status word figure 5-9 shows the configuration of the program status word. as shown in the figure, th program status word consists of a total of 5 bits including the lowest bit of system register address 7eh (rpl) and 4 bits of address 7fh (psw). each bit of the program status word has its own function. the 5 bits of the program status word are bcd flag (bcd), compare flag (cmp), carry flag (cy), zero flag (z), and index enable flag (ixe). figure 5-9. configuration of program status word 7eh rpl 0 0 retained 7fh psw 0 0 retained b 3 b 2 b 1 b 0 b c d b 3 c m p b 2 c y b 1 z b 0 i x e program status word (psword) address name symbol bit data clock stop reset by reset pin wdt&sp reset at reset
m pd17933, 17934 48 5.8.2 function of program status word the program status word is a register that sets the conditions under which the alu (arithmetic logic unit) executes an operation or data transfer, or indicates the result of an operation. table 5-2 outlines the function of each flag of the program status word. for details, refer to 7. alu (arithmetic logic unit) block . table 5-2. outline of function of each flag of program status word 5.8.3 cautions on using program status word when an arithmetic operation (addition or subtraction) is executed to the program status word, the result of the arithmetic operation is stored. for example, even if an operation that generates a carry is executed, if the result of the operation is 0000b, 0000b is stored to the psw. program status word (psword) rpl psw b 3 b 2 b 1 b 0 b c d b 3 c m p b 2 c y b 1 z b 0 i x e flag name index enable flag (ixe) zero flag (z) carry flag (cy) compare flag (cmp) bcd flag (bcd) function modifies address of data memory when data memory manipulation instruction is exeuted. 0 : does not modify 1 : modifies indicates result of arithmetic operation is zero. status of this flag differs depending on contents of compare flag. indicates occurrence of carry or borrow as result of execution of addition or subtraction instruction. this flag is reset to 0 if no carry or borrow occurs. it is set to 1 if carry or borrow occurs. this flag is also used as shift bit of ?orc r?instruction. indicates whether result of arithmetic operation is stored to data memory or general register. 0 : stores result. 1 : does not store result. indicates whether arithmetic operation is performed in decimal or binary. 0 : binary operation 1 : decimla operation (rp)
49 m pd17933, 17934 6. general register (gr) 6.1 outline of general register figure 6-1 outlines the general register. as shown in the figure, the general register is specified in the data memory by the general register pointer. the bank and row address of the general register are specified by the general register pointer. the general register is used to transfer or operate data between data memory addresses. figure 6-1. outline of general register column address bank2 bank1 bank0 data memory general register transfer, operation general register pointer system register bank15 bank14 row address bank3 remark address 5bh is not provided to bank4 through bank14. 6.2 general register the general register consists of 16 nibbles (16 4 bis) of the same row address on the data memory. for the range of the banks and row addresses that can be specified by the general register pointer as a general register, refer to 5.7 general register pointer (rp) . the 16 nibbles of the same row address specified as a general register operate or transfer data with the data memory by a single instruction. in other words, operation or data transfer between data memory addresses can be executed by a single instruction. the general register can be controlled by the data memory manipulation instruction, like the other data memory areas.
m pd17933, 17934 50 6.3 generating address of general register by each instruction the following sections 6.3.1 and 6.3.2 explain how the address of the general register is generated when each instruction is executed. for the details of the operation of each instruction, refer to 7. alu (arithmetic logic unit) block . 6.3.1 add (add r, m, addc r, m) , subtract (sub r, m, subc r, m) , logical operation (and r, m, or r, m, xor r, m), direct transfer (ld r, m, st m, r), and rotation (rorc r) instructions table 6-1 shows the address of the general register specified by operand r of an instruction. operand r of an instruction specifies only a column address. table 6-1. generating address of general register 6.3.2 indirect transfer (mov @r, m, mov m, @r) instruction table 6-2 shows a general register address specified by instruction operand r and an indirect transfer address specified by @r. table 6-2. generating address of general register 6.4 cautions on using general register 6.4.1 row address of general register because the row address of the general register is specified by the general register pointer, the currently specified bank may differ from the bank of the general register. 6.4.2 operation between general register and immediate data no instruction is available that executes an operation between the general register and immediate data. to execute an operation between the general register and immediate data, the general register must be treated as a data memory area. general register address column address row address bank b 3 b 2 b 1 b 0 b 2 b 1 b 0 b 3 b 2 b 1 b 0 r contents of general register pointer general register address indirect transfer address column address row address bank b 3 b 2 b 1 b 0 b 2 b 1 b 0 b 3 b 2 b 1 b 0 r contents of general register pointer contents of ? same as data memory
51 m pd17933, 17934 7. alu (arithmetic logic unit) block 7.1 outline of alu block figure 7-1 outlines the alu block. as shown in the figure, the alu block consists of an alu, temporary registers a and b, program status word, decimal adjustment circuit, and memory address control circuit. the alu operates on, judges, compares, rotates, and transfers 4-bit data in the data memory. figure 7-1. outline of alu block data bus address control data memory index modification memory pointer temporary register a temporary register b program status word carry/borrow/zero detection/decimal/storage specification alu ?arithmetic operation ?logical operation ?bit judgment ?comparison ?rotation ?transfer decimal adjustment
m pd17933, 17934 52 7.2 configuration and function of each block 7.2.1 alu the alu performs arithmetic operation, logical operation, bit judgment, comparison, rotation, and transfer of 4-bit data according to instructions specified by the program. 7.2.2 temporay registers a and b temporary registers a and b temporarily store 4-bit data. these registers are automatically used when an instruction is executed, and cannot be controlled by program. 7.2.3 program status word the program status word controls the operation of and stores the status of the alu. for further information on the program status word, also refer to 5.8 program status word (psword) . 7.2.4 decimal adjustment circuit the decimal adjustment circuit converts the result of an arithmetic operation into a decimal number if the bcd flag of the program status word is set to 1 during arthmetic operations. 7.2.5 address control circuit the address control circuit specifies an address of the data memory. at this time, address modification by the index register and data memory row address pointer is also controlled. 7.3 alu processing instruction list table 7-1 lists the alu operations when each instruction is executed. table 7-2 shows how data memory addresses are modified by the index register and data memory row address pointer. table 7-3 shows decimal adjustment data when a decimal operation is performed.
53 m pd17933, 17934 table 7-1. list of alu processing instruction operations alu instruction difference in operation depending on program status word (psword) address modification function value of value of operation operation of operation of z flag index memory bcd flag cmp flag cy flag pointer add add r, m 0 0 stores result of set if carry or set if result of operation modifies does not m, #n4 binary operation borrow occurs; is 0000b; otherwise, reset modify addc r, m 0 1 does not store result otherwise, reset retains status if result of operation m, #n4 of binary operation is 0000b; otherwise, reset subtract sub r, m 1 0 stores result of set if result of operation m, #n4 decimal operation is 0000b; otherwise, reset subc r, m 1 1 does not store result retains status if result of operation m, #n4 of decimal operation is 0000b; otherwise, reset logical or r, m dont care dont care not affected retains previous retains previous status modifies does not operation m, #n4 (retained) (retained) status modify and r, m m, #n4 xor r, m m, #n4 judge skt m, #n dont care dont care not affected retains previous retains previous status modifies does not skf m, #n (retained) (reset) status modify compare ske m, #n4 dont care dont care not affected retains previous retains previous status modifies does not skne m, #n4 (retained) (retained) status modify skge m, #n4 sklt m, #n4 transfer ld r, m dont care dont care not affected retains previous retains previous status modifies does not st m, r (retained) (retained) status modify mov m, #n4 @r, m modifies m, @r rotate rorc r dont care dont care not affected value of b 0 of retains previous status does not does not (retained) (retained) general register modify modify
m pd17933, 17934 54 table 7-2. modification of data memory address and indirect transfer address by index register and data memory row address pointer bank : bank register ix : index register ixe : index enable flag ixh : bits 10 through 8 of index register ixm : bits 7 through 4 of index register ixl : bits 3 through 0 of index register m : data memory address indicated by m r , m c m r : data memory row address (high-order) m c : data memory column address (low-order) mp : data memory row address pointer mpe : memory pointer enable flag r : general register column address rp : general register pointer ( ) : contents addressed by : direct address such as m and r b 3 b 2 b 1 b 0 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 2 b 1 b 0 b 3 b 2 b 1 b 0 general register address specified by ? data memory address specified by ? indirect transfer address specified by ?r bank row address column address bank row address column address bank row address column address rp r bank m bank m r (r) ditto mp (r) ditto bank m bank m r ix (r) or mp (r) ditto ditto ditto mpe 0 1 0 1 ixe 0 0 1 1 ixh, ixm logical or logical
55 m pd17933, 17934 table 7-3. decimal adjustment data operation hexadecimal addition decimal addition operation hexadecimal addition decimal addition result cy operation result cy operation result result cy operation result cy operation result 0 0 0000b 0 0000b 0 0 0000b 0 0000b 1 0 0001b 0 0001b 1 0 0001b 0 0001b 2 0 0010b 0 0010b 2 0 0010b 0 0010b 3 0 0011b 0 0011b 3 0 0011b 0 0011b 4 0 0100b 0 0100b 4 0 0100b 0 0100b 5 0 0101b 0 0101b 5 0 0101b 0 0101b 6 0 0110b 0 0110b 6 0 0110b 0 0110b 7 0 0111b 0 0111b 7 0 0111b 0 0111b 8 0 1000b 0 1000b 8 0 1000b 0 1000b 9 0 1001b 0 1001b 9 0 1001b 0 1001b 10 0 1010b 1 0000b 10 0 1010b 1 1100b 11 0 1011b 1 0001b 11 0 1011b 1 1101b 12 0 1100b 1 0010b 12 0 1100b 1 1110b 13 0 1101b 1 0011b 13 0 1101b 1 1111b 14 0 1110b 1 0100b 14 0 1110b 1 1100b 15 0 1111b 1 0101b 15 0 1111b 1 1101b 16 1 0000b 1 0110b C16 1 0000b 1 1110b 17 1 0001b 1 0111b C15 1 0001b 1 1111b 18 1 0010b 1 1000b C14 1 0010b 1 1100b 19 1 0011b 1 1001b C13 1 0011b 1 1101b 20 1 0100b 1 1110b C12 1 0100b 1 1110b 21 1 0101b 1 1111b C11 1 0101b 1 1111b 22 1 0110b 1 1100b C10 1 0110b 1 0000b 23 1 0111b 1 1101b C9 1 0111b 1 0001b 24 1 1000b 1 1110b C8 1 1000b 1 0010b 25 1 1001b 1 1111b C7 1 1001b 1 0011b 26 1 1010b 1 1100b C6 1 1010b 1 0100b 27 1 1011b 1 1101b C5 1 1011b 1 0101b 28 1 1100b 1 1010b C4 1 1100b 1 0110b 29 1 1101b 1 1011b C3 1 1101b 1 0111b 30 1 1110b 1 1100b C2 1 1110b 1 1000b 31 1 1111b 1 1101b C1 1 1111b 1 1001b remark decimal adjustment is not correctly carried out in the shaded area in the above table.
m pd17933, 17934 56 7.4 cautions on using alu 7.4.1 cautions on execution operation to program status word if an arithmetic operation is executed to the program status word, the result of the operation is stored to the program status word. the cy and z flags in the program status word are usually set or reset by the result of the arithmetic operation. if an arithmetic operation is executed to the program status word itself, the result of the operation is stored to the program status word, and consequently, it cannot be judged whether a carry or borrow occurs or whether the result of the operation is zero. if the cmp flag is set, however, the result of the operation is not stored to the program status word. therefore, the cy and z flags are set or reset normally. 7.4.2 cautions on executing decimal operation the decimal operation can be executed only when the result of the operation falls within the following ranges: (1) result of addition : 0 to 19 in decimal (2) result of subtraction: 0 to 9 or C10 to C1 in decimal if a decimal operation is executed exceeding or falling below the above ranges, the result is a value greater than 1010b (0ah).
57 m pd17933, 17934 8. register file (rf) and control registers 8.1 outline of register file figure 8-1 outlines the register file. as shown in the figure, the rgister file consists of the control registers existing on addresses 00h through 3fh of bank15 in the data memory, and a portion overlapping the data memory specified by the bank register. the control registers set conditions of the peripheral hardware units. the data on the register file can be read or written via window register. figure 8-1. outline of register file control register (00h-3fh of bank15 in data memory) (same space as data memory specified by bank register) data manipulation via window register 0 1 2 3 4 5 6 7 system register window re g ister peripheral hardware register file row address
m pd17933, 17934 58 8.2 configuration and function of register file figure 8-2 shows the configuration of the register file and the relationships between the register file and data memory. the register file is assigned addresses in 4-bit units, like the data memory, and consists of a total of 128 nibbles with row addresses 0h through 7fh and column addresses 0h through 0fh. addresses 00h through 3fh are overlapping addresses 00h through 3fh of bank15 and called control registers that sets the conditions of the peripheral hardware units. addresses 40h through 7fh overlap the data memory specified by the bank register. in other words, addresses 40h through 7fh of the register file are addresses 40h through 7fh of the currently-selected bank of data memory. addresses 40h through 7fh of the register file can be manipulated in the same manner as the data memory, except that the addresses of the register file can also be manipulated by using register file manipulation instructions (peek wr, rf and poke rf, wr). note, however, that addresses 40h through 6fh of bank15 are assigned control register including port input/output selection registers (for details refer to 8.3 control registers and input/output selection registers ). addresses 5ch through 6fh of bank14 are assigned lcd segment register (for details, refer to 8.4 lcd segment register ). figure 8-2. configuration of register file and relationship with data memory column address 0 1 2 3 4 5 6 7 01 234 56789abcdef system registers 0 1 2 3 bank15 (control registers) data memory bank0 bank1 bank2 bank14 register file bank15 (control register) port input/output selection registers row address bank3 lcd segment register caution never write anything to address 31h of bank15 because this address is a test mode area. remark address 5bh is not provided to bank4 through bank14.
59 m pd17933, 17934 8.2.1 register file manipulation instructions (peek wr, rf, poke rf, wr) data is read from or written to the register file via the window register of the system registers, by using the following instructions. (1) peek wr, rf reads data of the register file addressed by rf to the window register. (2) poke rf, wr writes the data of the window register to the register file addressed by rf. 8.3 control registers and input/output selection registers figure 8-3 shows the configuration of the control registers. the control registers, including the input/output select registers, consist of a total of 112 nibbles (112 x 4 bits) at addresses 00h through 6fh of bank15 of the data memory. of these addresses, 00h through 3fh overlap addresses 00h through 3fh of the register file. addresses 60h through 6fh are assigned the input/output select registers. however, only 38 nibbles of the control registers are actually used. the remaining 14 nibbles are unused registers and prohibited from being written or read. each control register has an attribute of 1 nibble that identifies four types of registers: read/write (r/w), read- only (r), write-only (w), and read-and-reset (r&reset) registers. nothing is changed even if data is written to a read-only (r and r&reset) register. an undefined value is read if a write-only (w) register is read. among the 4-bit data in 1 nibble, the bit fixed to 0 is always 0 when it is read, and is also 0 when it is written. the 74 nibbles of unused registers are undefined when their contents are read, and nothing changes even when they are written. never write anything to address 31h of bank15 because this address is a test mode area. table 8-1 lists the peripheral hardware control functions of the control registers.
m pd17933, 17934 60 figure 8-3. configuration of control registers (addresses 00h-3fh) (1/4) notes 1. ( ) indicates an address that is used when the assembler is used. 2. never write anything to address 20h of bank15. 3. never write anything to address 31h of bank15 because this address is a test mode area. (bank15) column address row address item 1234 567 0 (8) note1 1 (9) note1 2 (a) note1 3 (b) note1 name symbol read/ write name symbol read/ write name symbol read/ write name symbol read/ write stack pointer watchdog timer clock selection watchdog timer counter reset data buffer stack pointer stack overflow/ underflow reset selection movt bit selection ( ) s p 3 ( ) s p 2 ( ) s p 1 ( ) s p 0 00w d t c k 1 w d t c k 0 w d t r e s 00000 ( ) d b f s p 1 ( ) d b f s p 0 00s p r s e l 1 s p r s e l 0 00m o v t s e l 1 m o v t s e l 0 r/w r/w w & reset r r/w r/w 0 pll mode selection pll reference frequency selection pll unlock ff beep clock selection watchdog timer/stack pointer reset status detection basic timer 0 carry 0p l l m d 0 p l l m d 1 p l l s c n f 0p l l r f c k 1 p l l r f c k 2 p l l r f c k 0 000p l l u l 0b e e p 0 s e l b e e p 0 c k 1 b e e p 0 c k 0 000w d t s p r e s 000b t m 0 c y r/w r & reset r/w r & reset r/w r & reset if counter gate status detection if counter mode selection if counter control a/d converter channel selection a/d converter mode selection 0i f c g o s t t 0 0i f c m d 1 i f c m d 0 i f c c k 1 i f c c k 0 00 i f c s t r t i f c r e s 00a d c c h 1 a d c c h 0 f c g c h 0 0 0 000a d c s t r t a d c c m p r/w r r/w r/w r/w w note 2 r note 3
61 m pd17933, 17934 figure 8-3. configuration of control register (address 00h-3fh) (2/4) note ( ) indicates an address that is used when the assembler is used. 9abcdef system register interrupt stack pointer 0 ( ) s y s r s p 0 r 8 basic timer 1 clock selection serial i/o1 mode selection interrupt edge selection 0b t m 1 c k 0 0 000s i o 1 c k 1 s i o 1 c k 0 000i e g 0 r/w r/w r/w timer 0 counter clock selection timer 0 mode selection interrupt enable 1 t m 0 e n t m 0 r e s t m 0 c k 1 t m 0 c k 0 t m 0 o v f 000i p s i o 1 i p s i o 0 i p t m 3 i p t m 2 r/w r/w r/w r/w r/w 0s i o 1 m o d s i o 1 h i z s i o 1 t s serial i/o1 clock r/w interrupt enable 2 interrupt enable 3 serial interface 1 interrupt request basic interval timer 1 interrupt request timer 0 interrupt request int0 pin interrupt request 000 i r q s i o 1 000 i r q b t m 1 000 i r q t m 0 i n t 0 00 i r q 1 r/w r/w r/w r/w i p 0 i p c e i p 2 i p 1 i p 4 i p 3 i p t m 1 i p t m 0 ( ) s y s r s p 1 ( ) s y s r s p 2
m pd17933, 17934 62 figure 8-3. configuration of control register (addresses 40h-6fh) (3/4) (bank15) column address row address item 1234 567 4 5 6 name symbol read/ write 1 name symbol read/ write name symbol read/ write lcd driver display start r/w 0 l c d d b c k 00l c d e n note note bit 3 of address 40h of bank15 is a test mode area, therefore, do not write 1 to bit 3.
63 m pd17933, 17934 figure 8-3. configuration of control register (addresses 40h-6fh) (4/4) 9abcdef 8 port 2c bit i/o selection port 2b bit i/o selection p 2 c b i o 3 p 2 c b i o 2 p 2 c b i o 1 p 2 c b i o 0 p 2 b b i o 3 p 2 b b i o 2 p 2 b b i o 1 p 2 b b i o 0 p 1 d b i o 3 p 1 d b i o 2 p 1 d b i o 1 p 1 d b i o 0 r/w r/w r/w r/w r/w port 1a bit i/o selection port 0b bit i/o selection p 0 b b i o 1 p 0 b b i o 0 p 0 b b i o 3 p 0 b b i o 2 p 1 a b i o 1 p 1 a b i o 0 p 1 a b i o 3 p 1 a b i o 2 r/w r/w p 0 d p l d 3 p 0 d p l d 2 p 0 d p l d 1 p 0 d p l d 0 0l c d 1 9 s e l l c d 1 8 s e l l c d 1 7 s e l port 0d pull-down resistor lcd port selection port 1d bit i/o selection
m pd17933, 17934 64 table 8-1. peripheral hardware control functions of control registers (1/5) peripheral control register peripheral hardware control function at reset clock hardware name address read/ function set value reset by wdt stop (bank15) write symbol reset & sp 01 pin reset stack stack pointer 01h r/w (sp3) ff retained (sp2) (sp1) (sp0) interrupt stack 08h r 0 55 retained pointer of (sysrsp2) system register (sysrsp1) (sysrsp0) data buffer 04h r 0 fixed to 0 0 0 retained stack pointer 0 (dbfsp1) detects nesting level (dbfsp0) of data buffer stack stack overflow/ 05h r/w 0 fixed to 0 3 retained retained underflow reset 0 selection sprsel1 selects interrupt stack reset reset valid overflow/underflow reset prohibited (can be set only once following power application) sprsel0 selects address stack overflow/underflow reset (can be set only once following power application) watchdog watchdog timer 02h r/w 0 fixed to 0 3 retained retained timer clock selection 0 wdtck1 selects clock of watchdog timer (can be wdtck0 set only once following power application) watchdog timer 03h w & wdtres resets watchdog timer counter invalid reset if written undefined undefined undefined counter reset reset 0 fixed to 0 0 0 wdt&sp reset 16h r & 0 01 retained status detection reset 0 0 wdtspres detects resetting of watchdog no reset reset request timer/stack pointer request b 3 b 2 b 1 b 0 0011 level 0 level 1 level 2 level 3 0101 00 1 1 not 4096 setting 8192 used instruction prohibited instruction 01 0 1
65 m pd17933, 17934 table 8-1. peripheral hardware control functions of control registers (2/5) peripheral control register peripheral hardware control function at reset clock hardware name address read/ function set value reset by wdt stop (bank15) write symbol reset & sp 01 pin reset movt movt bit 07h r/w 0 fixed to 0 0 0 retained selection 0 movtsel1 sets bit transferred by movt (transferred movtsel0 to 0eh and 0fh only during 8-bit transfer) serial serial i/o1 1ch r/w 0 fixed to 0 0 0 0 interface clock selection 0 sio0ck1 sets internal clck of serial sio0ck0 interface 1 serial i/o1 1dh r/w 0 fixed to 0 0 0 0 mode selection sio1mod sets si1/so2 pin switching si1 so2 sio1hiz sets p0b2/so1 pin status general i/o port serial data output pin sio1ts starts or stops operation stops operation starts operation pll pll mode 10h r/w pllscnf sets low-order bits of swallow counter lsb is 0 lsb is 1 undefined undefined retained frequency selection 0 fixed to 0 0 0 0 synthesizer pllmd1 sets division mode of pll pllmd0 pll reference 11h r/w 0 fixed to 0 7 7 7 frequency pllrfck2 sets reference frequency of pll selection pllrfck1 pllrfck0 pll unlcok ff 12h r & 0 fixed to 0 undefined undefined retained reset 0 0 pllul detects status of unlock ff locked unclocked beep beep/general- 14h r/w 0 fixed to 0 0 0 0 purpose port pin beep0sel selects function of p0b3/beep pin general-purpose beep function selection i/o port beep0ck1 sets beep pin beep0ck0 timer basic timer 17h r & 0 fixed to 0 0 retained retained 0 carry reset 0 0 btm0cy detects basic timer 0 carry ff ff reset ff set 00 0 1 16-bit high-order low-order transfer 8-bit transfer 8-bit transfer 01 1 0 0011 external 125 18.75 37.5 clock khz khz khz (75 khz) 0101 b 3 b 2 b 1 b 0 0: 1 khz 1: 3 khz 2: 5 khz 3: 6.25 khz 4: 12.5 khz 5: 25 khz 6: setting prohibited 7: setting prohibited 0011 disabled mf vhf hf 0101 00 11 low level high level 1.5 khz 3 khz output output 01 01
m pd17933, 17934 66 table 8-1. peripheral hardware control functions of control registers (3/5) peripheral control register peripheral hardware control function at reset clock hardware name address read/ function set value reset by wdt stop (bank15) write symbol reset & sp 01 pin reset timer basic timer 1 18h r/w 0 fixed to 0 0 0 retained clock selection 0 0 btm1ck0 selects clock of basic timer 0 31.25 hz (32 ms) 125 hz (8 ms) timer 0 counter 2bh r/w tm0en starts or stops timer 0 counter stops starts 0 0 0 clock selection tm0res resets timer 0 counter not affected reset tm0ck1 sets basic clock of timer tm0ck0 0 counter timer 0 mode 2ch r/w tm0ovf detects timer 0 overflow no overflow overflow 0 0 0 selection tm0gceg sets edge of gate close input rising edge falling edge signal tm0goeg sets edge of gate open input signal tm0md selects modulo counter/gate modulo counter gate counter counter of timer 0 interrupt interrupt edge 1fh r/w 0 fixed to 0 0 0 retained selection 0 0 ieg0 sets interrupt issuance edge rising edge falling edge (int pin) interrupt enable 2fh r/w ipsio1 enables serial interface 1 disables enables 0 0 retained interrupt interrupt interrupt ipbtm1 enables basic interface timer 1 interrupt iptm0 enables timer 0 interrupt ip0 enables int pin interrupt serial interface 1 3ch r/w 0 fixed to 0 0 0 retained interrupt request 0 0 irqsio1 detects serial interface 1 no interrupt interrupt interrupt request request request b 3 b 2 b 1 b 0 0011 tm0 tm1 75 khz 25 khz (13.3 m s) (40 m s) 0101
67 m pd17933, 17934 table 8-1. peripheral hardware control functions of control registers (4/5) peripheral control register peripheral hardware control function at reset clock hardware name address read/ function set value reset by wdt stop (bank15) write symbol reset & sp 01 pin reset interrupt basic interval 3dh r/w 0 fixed to 0 0 0 retained timer 1 0 interrupt request 0 irqbtm1 detects basic interval timer 1 no interrupt request interrupt request interrupt request timer 0 interrupt 3eh r/w 0 fixed to 0 0 0 retained request 0 0 irqtm0 detects timer 0 interrupt request no interrupt request interrupt request int0 pin interrupt 3fh r/w int0 detects int0 pin status low level high level undefined undefined undefined request 0 fixed to 0 0 0 retained 0 irq0 detects int0 pin interrupt request no interrupt request interrupt request if 20h r/w 0 fixed to 0 0 0 0 counter 0 0 fcgch0 note 1 note 1 if counter gate 21h r 0 fixed to 0 0 0 0 status detection 0 0 ifcgostt detects if counter gate status closed open if counter 22h r/w ifcmd1 sets if counter mode 0 0 0 mode selection ifcmd0 ifcck1 sets if counter gate time ifcck0 if counter 23h w 0 fixed to 0 0 0 0 control 0 ifcstrt starts or stops if counter nothing affected starts counter ifcres resets if counter data nothing affected resets counter a/d a/d converter 24h r/w 0 fixed to 0 0 0 retained converter channel 0 selection adcch1 selects pin used for a/d converter adcch0 b 3 b 2 b 1 b 0 0011 1ms 4 ms 8 ms open 0101 0: a/d converter not used 1: p0d1/ad0 pin 2: p0d2/ad1pin 3: p0d3/ad2 pin 0011 general- amifc fmifc amifc2 purpose input port 0101
m pd17933, 17934 68 table 8-1. peripheral hardware control functions of control registers (5/5) peripheral control register peripheral hardware control function at reset clock hardware name address read/ function set value power- wdt stop (bank15) write symbol on & sp 01 reset reset a/d a/d converter 25h r 0 fixed to 0 0 0 0 converter mode selection 0 adcstrt detects operating status of conversion ends converting a/d converter adccmp detects comparison result of v adcref > v adcin v adcref < v adcin retained a/d converter lcd lcd driver 40h r/w lcddbck note 2 note 2 00 0 driver display start 0 fixed to 0 0 lcden sets on/off of all the lcd display display off display on lcd port 69h r/w 0 fixed to 0 0 0 0 selection lcd19sel selects function of p2a2/lcd19 pin general- lcd 0 0 retained lcd18sel selects function of p2a2/lcd18 pin purpose segment lcd17sel selects function of p2a2/lcd17 pin input port input/ port 0d pull- 6ah r/w p0dpld3 selects pull-down resistor of p0d3 pin pull-down pull-down 00 retained output down resistor p0dpld2 selects pull-down resistor of p0d2 pin resistor used resistor not used port selection p0dpld1 selects pull-down resistor of p0d1 pin p0dpld0 selects pull-down resistor of p0d0 pin port 2c bit i/o 6bh r/w p2cbio3 selects i/o of port p2c3 input output 0 0 retained selection p2cbio2 selects i/o of port p2c2 p2cbio1 selects i/o of port p2c1 p2cbio0 selects i/o of port p2c0 port 2b bit i/o 6ch r/w p2bbio3 selects i/o of port p2b3 input output 0 0 retained selection p2bbio2 selects i/o of port p2b2 p2bbio1 selects i/o of port p2b1 p2bbio0 selects i/o of port p2b0 port 1d bit i/o 6dh r/w p1dbio3 selects i/o of port p1d3 input output 0 0 retained selection p1dbio2 selects i/o of port p1d2 p1dbio1 selects i/o of port p1d1 p1dbio0 selects i/o of port p1d0 port 1a bit i/o 6eh r/w p1abio3 selects i/o of port p1a3 input output 0 0 retained selection p1abio2 selects i/o of port p1a2 p1abio1 selects i/o of port p1a1 p1abio0 selects i/o of port p1a0 port 0b bit i/o 6fh r/w p0bbio3 selects i/o of port p0b3 input output 0 0 retained selection p0bbio2 selects i/o of port p0b2 p0bbio1 selects i/o of port p0b1 p0bbio0 selects i/o of port p0b0 notes 1. never write anything to address 20h of bank15. 2. bit 3 of address 40h of bank15 is a test mode area, therefore, do not write 1 to bit 3. b 3 b 2 b 1 b 0
69 m pd17933, 17934 8.4 lcd segment registers the lcd segment registers consist of a total of 20 nibbles (20 x 4 bits) of addresses 5ch through 6fh of bank14 of the data memory. for details, refer to 19. lcd controller/driver . 8.5 cautions on using control register keep in mind the following points (1) through (4) when using the write-only (w), read-only (r), and unused registers of the control registers (addresses 00h through 6fh of bank15. (1) an undefined value is read if a write-only register is read. (2) nothing is affected even if a read-only register is written. (3) an undefined value is read if an unused register is read. nor is anything affected if this register is written. (4) never write anything to address 31h of bank15 because this address is a test mode area.
m pd17933, 17934 70 9. data buffer (dbf) 9.1 outline of data buffer figure 9-1 outlines the data buffer. the data buffer is located on the data memory and has the following two functions. ? reads constant data on the program memory (table reference) ? transfers data with the peripheral hardware units figure 9-1. outline of data buffer data buffer data write (put) data read (get) table reference (movt) peripheral hardware constant data program memory
71 m pd17933, 17934 9.2 data buffer 9.2.1 configuration of data buffer figure 9-2 shows the configuration of the data buffer. as shown in the figure, the data buffer consists of a total of 16 bits of addresses 0ch through 0fh of bank 0 on the data memory. the 16-bit data is configured with bit 3 of address 0ch as the msb and bit 0 of address 0fh as the lsb. because the data buffer is located on the data memory, it can be manipulated by all data memory manipulation instructions. figure 9-2. configuration of data buffer column address 0 1 2 3 4 5 6 7 0123456789abcdef bank0 bank1 bank2 bank14 bank15 system register address bit bit signal data b 3 b 15 b 2 b 14 b 1 b 13 b 0 b 12 dbf3 0ch b 3 b 11 b 2 b 10 b 1 b 9 b 0 b 8 dbf2 0dh b 3 b 7 b 2 b 6 b 1 b 5 b 0 b 4 dbf1 0eh b 3 b 3 b 2 b 2 b 1 b 1 b 0 b 0 dbf0 0fh data memory data buffer data buffer (dbf) row address data memory m s b ? l s b ? data bank3 remark address 5bh is not provided to bank4 through bank14.
m pd17933, 17934 72 9.2.2 table reference instruction (movt dbf, @ar) this instruction moves the contents of the program memory addressed by the contents of the address register to the data buffer. the number of bits transferred by the table reference instruction can be specified by movt selection register (address 07h) of the control registers. when 8-bit data is transferred, it is read to dbf1 and 0. when the table reference instruction is used, one stack level is used. all the addresses of the program memory can be referenced by the table reference instruction. 9.2.3 peripheral hardware control instructions (put and get) the operations of the put and get instructions are as follows: (1) get dbf, p reads the data of a peripheral register addressed by p to the data buffer. (2) put p, dbf sets the data of the data buffer to a peripheral register addressed by p. 9.3 relationships between peripheral hardware and data buffer table 9-1 shows the relationships between the peripheral hardware and the data buffer.
73 m pd17933, 17934 memo
m pd17933, 17934 74 table 9-1. relationships between peripheral hardware and data buffer (1/2) peripheral hardware peripheral register transferring data with data buffer name symbol peripheral execution of i/o actual address put/get bit bit instruction a/d converter a/d converter data register adcr 02h put/get 8 8 serial interface 1 presettable shift register 1 sio1sfr 04h put/get 8 8 timer 0 timer 0 modulo register tm0m 1ah put/get 8 8 timer 0 counter tm0c 1bh get 8 8 address register address register ar 40h put/get 16 16 data buffer stack dbf stack dbfstk 41h put/get 16 16 pll frequency synthesizer note pll data register pllr 42h put/get 16 16 frequency counter ifc data register ifc 43h get 16 16 note the programmable counter of the pll frequency synthesizer is configured of 17 bits, of which the high- order 16 bits indicate the pll data register (pllr) and the low-order bits are allocated to the pllscnf flag (the third bit of address 10h). for details, refer to 16. pll frequency synthesizer .
75 m pd17933, 17934 table 9-1. relationships between peripheral hardware and data buffer (2/2) at reset clock function reset by wdt&sp stop reset pin reset 0 0 retained sets compare voltage v adcref of a/d converter undefined undefined retained sets serial-out data and reads serial-in data ff ff ff sets modulo register value of timer 0 0 0 0 reads count value of timer 0 counter 0 0 retained transfers data with address register undefined undefined retained saves data of data buffer undefined undefined retained sets division value (n value) of pll 0 0 0 reads count value of frequency counter
m pd17933, 17934 76 9.4 cautions on using data buffer keep the following points in mind concerning the unused peripheral addresses, write-only peripheral register (put only), and read-only peripheral register (get only) when transferring data with the peripheral hardware via data buffer. ? an undefined value is read if a write-only register is read. ? nothing is affected even if a read-only register is written. ? an undefined value is read if an unused address is read. nor is anything affected if this address is written.
77 m pd17933, 17934 10. data buffer stack 10.1 outline of data buffer stack figure 10-1 outlines the data buffer stack. as shown in the figure, the data buffer stack consists of a data buffer stack pointer and data buffer stack registers. the data buffer stack saves or restores the contents of the data buffer when the put or get instruction is executed. therefore, the contents of the data buffer can be saved by one instruction when an interrupt is accepted. figure 10-1. outline of data buffer stack 10.2 data buffer stack register figure 10-2 shows the configuration of the data buffer stack registers. as shown in the figure, the data buffer stack registers consist of four 16-bit registers. the contents of the data buffer are saved by executing the put instruction, and the saved data is restored by executing the get instruction. the data buffer contents can be successively saved up to 4 levels. data buffer stack pointer dbf data buffer stack registers address specification
m pd17933, 17934 78 figure 10-2. configuration of data buffer stack register dbf3 dbf2 dbf1 dbf0 16 bits data buffer transfer data valid data b 15 b 14 b 13 b 12 b 11 b 10 b 9 b 8 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 data buffer stack register dbfstk 41h get put saves contents of data buffer up to 4 levels bit name symbol address data
79 m pd17933, 17934 10.3 data buffer stack pointer the data buffer stack pointer detects the multiplexing level of the data buffer stack registers. when the put instruction is executed to the data buffer stack, the value of the data buffer stack pointer is incremented by one; when the get instruction is executed, the value of the pointer is decremented by one. the data buffer stack pointer can be only read and cannot be written. the configuration and function of the data buffer stack pointer are illustrated below. name flag symbol b 3 0 b 2 0 b 1 d b f s p 1 b 0 d b f s p 0 address 04h read/write r data buffer stack pointer reset by reset pin wdt&sp reset clock stop 0 1 0 1 level 0 level 1 level 2 level 3 detects multiplexing level of data buffer stack 0 0 1 1 retained fixed to ? 000 0 0 0 at reset
m pd17933, 17934 80 10.4 operation of data buffer stack figure 10-3 shows the operation of the data buffer stack. as shown in the figure, when the put instruction is executed, the contents of the data buffer are transferred to a data buffer stack register specified by the stack pointer, and the stack pointer is incremented by one. when the get instruction is executed, the contents of a data buffer stack register specified by the stack pointer are transferred to the data buffer, and the stack pointer is decremented by one. therefore, note that the value of the stack pointer is set to 1 if data has been written once because its initial value is 0, and that the stack pointer is set to 0 when data has been written four times. note that when writing (put) exceeding four levels, the first data are discarded. figure 10-3. operation of data buffer stack (a) if writing does not exceed level 4 (b) if writing exceeds level 4 undefined undefined undefined undefined v dd a undefined undefined undefined put a b undefined undefined put a b undefined undefined get a b undefined undefined get 0 1 2 3 a undefined undefined undefined put a b undefined undefined put a b c undefined put a b c d e b c d e b c d get e b c d get put put 0 1 2 3
81 m pd17933, 17934 10.5 using data buffer stack a program example is shown below. example to save the contents of the data buffer and address register by using int0 interrupt routine (the contents of the data buffer and address register are not automatically saved when an interrupt occurs). start: br initial ; reset address ; interrupt vector address nop ; si0 nop ; basic timer 1 nop ; tm0 intint: ; int pin interrupt vector address (0004h) put dbfstk, dbf ; saves contents of dbf to first level of data buffer ; stack (dbfstk) get dbf, ar ; transfers contents of address register (ar) to dbf put dbfstk, dbf ; saves contents of ar to second level of data buffer ; stack processing b ; int interrupt processing get dbf, dbfstk ; restores second level of data buffer stack to data buffer, put ar, dbf ; and restores contents of data buffer to address register get dbf, dbfstk ; restores first level of data buffer stack to data buffer ei reti initial: set1 ip0 ei loop: processing a br loop end 10.6 cautions on using data buffer stack the contents of the data buffer stack are not automatically saved when an interrupt is accepted, and therefore, must be saved by software. even when a bank of the data memory other than bank0 is specified, the contents of the data buffer (existing in bank0) can be saved or restored by using the put and get instructions.
m pd17933, 17934 82 11. general-purpose port the general-purpose ports output high-level, low-level, or floating signals to external circuits, and read high- level or low-level signals from external circuits. 11.1 outline of general-purpose port table 11-1 shows the relationships between each port and port register. the general-prupose ports are classified into i/o, input, and output ports. the i/o ports can be set in the input or output mode in 1-bit (1-pin) units. the inut or output mode of each i/o port is specified by the port input/output selection registers (addresses 60h through 6fh) of bank15. table 11-1. relationships between port (pin) and port register (1/2) port pin data setting method no. symbol i/o port register (data memory) bank address symbol bit symbol (reserved word) port 0a no pin output bank0 70h p0a b 3 C no pin b 2 C 19 p0a1 b 1 p0a1 18 p0a0 b 0 p0a0 port 0b 31 p0b3 i/o (bit i/o) 71h p0b b 3 p0b3 30 p0b2 b 2 p0b2 29 p0b1 b 1 p0b1 28 p0b0 b 0 p0b0 port 0c 67 p0c3 output 72h p0c b 3 p0c3 66 p0c2 b 2 p0c2 65 p0c1 b 1 p0c1 64 p0c0 b 0 p0c0 port 0d 78 p0d3 input 73h p0d b 3 p0d3 77 p0d2 b 2 p0d2 76 p0d1 b 1 p0d1 75 p0d0 b 0 p0d0
83 m pd17933, 17934 table 11-1. relationships between port (pin) and port register (2/2) port pin data setting method no. symbol i/o port register (data memory) bank address symbol bit symbol (reserved word) port 1a 23 p1a3 i/o (bit i/o) bank1 70h p1a b 3 p1a3 22 p1a2 b 2 p1a2 21 p1a1 b 1 p1a1 20 p1a0 b 0 p1a0 port 1c 4 p1c3 input 72h p1c b 3 p1c3 3 p1c2 b 2 p1c2 2 p1c1 b 1 p1c1 1 p1c0 b 0 p1c0 port 1d 27 p1d3 i/o (bit i/o) 73h p1d b 3 p1d3 26 p1d2 b 2 p1d2 25 p1d1 b 1 p1d1 24 p1d0 b 0 p1d0 port 2a no pin input bank2 70h p2a b 3 C 63 p2a2 b 2 p2a2 62 p2a1 b 1 p2a1 61 p2a0 b 0 p2a0 port 2b 17 p2b3 i/o (bit i/o) 71h p2b b 3 p2b3 16 p2b2 b 2 p2b2 15 p2b1 b 1 p2b1 14 p2b0 b 0 p2b0 port 2c 74 p2c3 i/o 72h p2c b 3 p2c3 73 p2c2 (bit i/o) b 2 p2c2 72 p2c1 b 1 p2c1 71 p2c0 b 0 p2c0 C no pin C bank3 70h-73h C fixed to 0 | bank15 note note address 5bh is not provided to bank4 through bank14.
m pd17933, 17934 84 11.2 general-purpose i/o port (p0b, p1a, p1d, p2b, p2c) 11.2.1 configuration of i/o port the following paragraphs (1) and (2) show the configuration of the i/o ports. (1) p0b (p0b3, p0b2, p0b1, p0b0) p2b (p2b3, p2b2, p2b1, p2b0) p2c (p2c3, p2c2, p2c1, p2c0) v dd v dd i/o selection flag output latch 1 0 read instruction port register (1 bit) write instruction
85 m pd17933, 17934 (2) p1a (p1a3, p1a2, p1a1, p1a0) p1d (p1d3, p1d2, p1d1, p1d0) 11.2.2 using i/o port the input or output mode of the i/o ports is set by i/o selection register p0b, p1a, p1d, p2b or p2c of the control registers. because these are bit i/o ports, they can be set in the input or output mode in 1-bit units. setting the output data of or reading the input data of a port is carried out by executing an instruction that writes data to or reads data from the port. 11.2.3 shows the configuration of the i/o selection register of each port. 11.2.4 and 11.2.5 describe how each port is used as an input or output port. 11.2.6 describes the reset status of the i/o ports. v dd i/o selection flag output latch read instruction port register (1 bit) write instruction 1 0
m pd17933, 17934 86 11.2.3 i/o port i/o selection register the following i/o selection registers of the i/o ports are available. ? port 0b bit i/o selection register ? port 1a bit i/o selection register ? port 1d bit i/o selection register ? port 2b bit i/o selection register ? port 2c bit i/o selection register each i/o selection register sets the input or output mode of the corresponding port pin. the following paragraphs (1) through (5) descibe the configuration and functions of the above i/o selection registers.
87 m pd17933, 17934 (1) port 0b bit i/o selection register name flag symbol b 3 p 0 b b i o 3 b 2 p 0 b b i o 2 b 1 p 0 b b i o 1 b 0 p 0 b b i o 0 address (bank15) 6fh read/write r/w port 0b bit i/o selection reset by reset pin wdt&sp reset clock stop 0 1 sets p0b0 pin in input mode sets p0b0 pin in output mode sets input/output mode of port retained sets p0b1 pin in input mode sets p0b1 pin in output mode sets input/output mode of port 0 1 sets p0b2 pin in input mode sets p0b2 pin in output mode sets input/output mode of port 0 1 sets p0b3 pin in input mode sets p0b3 pin in output mode sets input/output mode of port 0 1 0 0 0 0 0 0 0 0 at reset
m pd17933, 17934 88 (2) port 1a bit i/o selection register name flag symbol b 3 p 1 a b i o 3 b 2 p 1 a b i o 2 b 1 p 1 a b i o 1 b 0 p 1 a b i o 0 address (bank15) 6eh read/write r/w port 1a bit i/o selection reset by reset pin wdt&sp reset clock stop 0 1 sets p1a0 pin in input mode sets p1a0 pin in output mode sets input/output mode of port retained sets p1a1 pin in input mode sets p1a1 pin in output mode sets input/output mode of port 0 1 sets p1a2 pin in input mode sets p1a2 pin in output mode sets input/output mode of port 0 1 sets p1a3 pin in input mode sets p1a3 pin in output mode sets input/output mode of port 0 1 0 0 0 0 0 0 0 0 at reset
89 m pd17933, 17934 (3) port 1d bit i/o selection register name flag symbol b 3 p 1 d b i o 3 b 2 p 1 d b i o 2 b 1 p 1 d b i o 1 b 0 p 1 d b i o 0 address (bank15) 6dh read/write r/w port 1d bit i/o selection reset by reset pin wdt&sp reset clock stop 0 1 sets p1d0 pin in input mode sets p1d0 pin in output mode sets input/output mode of port retained sets p1d1 pin in input mode sets p1d1 pin in output mode sets input/output mode of port 0 1 sets p1d2 pin in input mode sets p1d2 pin in output mode sets input/output mode of port 0 1 sets p1d3 pin in input mode sets p1d3 pin in output mode sets input/output mode of port 0 1 0 0 0 0 0 0 0 0 at reset
m pd17933, 17934 90 (4) port 2b bit i/o selection register name flag symbol b 3 p 2 b b i o 3 b 2 p 2 b b i o 2 b 1 p 2 b b i o 1 b 0 p 2 b b i o 0 address (bank15) 6ch read/write r/w port 2b bit i/o selection reset by reset pin wdt&sp reset clock stop 0 1 sets p2b0 pin in input mode sets p2b0 pin in output mode sets input/output mode of port retained sets p2b1 pin in input mode sets p2b1 pin in output mode sets input/output mode of port 0 1 sets p2b2 pin in input mode sets p2b2 pin in output mode sets input/output mode of port 0 1 sets p2b3 pin in input mode sets p2b3 pin in output mode sets input/output mode of port 0 1 0 0 0 0 0 0 0 0 at reset
91 m pd17933, 17934 (5) port 2c bit i/o selection register name flag symbol b 3 p 2 c b i o 3 b 2 p 2 c b i o 2 b 1 p 2 c b i o 1 b 0 p 2 c b i o 0 address (bank15) 6bh read/write r/w port 2c bit i/o selection reset by reset pin wdt&sp reset clock stop 0 1 sets p2c0 pin in input mode sets p2c0 pin in output mode sets input/output mode of port retained sets p2c1 pin in input mode sets p2c1 pin in output mode sets input/output mode of port 0 1 sets p2c2 pin in input mode sets p2c2 pin in output mode sets input/output mode of port 0 1 sets p2c3 pin in input mode sets p2c3 pin in output mode sets input/output mode of port 0 1 0 0 0 0 0 0 0 0 at reset
m pd17933, 17934 92 11.2.4 when using i/o port as input port the port pin to be set in the input mode is selected by the i/o selection register corresponding to the port. ports p0b, p1a, p1d, p2b and p2c can be set in the input or output mode in 1-bit units. the pin set in the input mode is floated (hi-z) and waits for input of an external signal. the input data is read by executing a read instruction (such as skt) to the port register corresponding to the port pin. 1 is read from the port register when a high level is input to the corresponding port pin; when a low level is input to the port pin, 0 is read from the register. when a write instruction (such as mov) is executed to the port register corresponding to the pin set in the input mode, the contents of the output latch are rewritten. 11.2.5 when using i/o port as output port the port pin to be set in the output mode is selected by the i/o selection register corresponding to the port. ports p0b, p1a, p1d, p2b and p2c can be set in the input or output mode in 1-bit units. the pin set in the output mode outputs the contents of the output latch. the output data is set by executing a write instruction (such as mov) to the port register corresponding to the port pin. write 1 to the port register to output a high level to the port pin; write 0 to output a low level. the port pin can be also floated (hi-z) if it is set in the input mode. if a read instruction (such as skt) is executed to the port register corresponding to a port pin set in the output mode, the contents of the output latch are read. 11.2.6 status of i/o port at reset (1) at reset by reset pin all the i/o ports are set in the input mode. the contents of the output latch are reset to 0. (2) at wdt&sp reset all the i/o ports are set in the input mode. the contents of the output latch are reset to 0. (3) on execution of clock stop instruction the setting of the input or output mode is retained. the contents of the output latch are also retained. (4) in halt status the previous status is retained.
93 m pd17933, 17934 11.3 general-purpose input port (p0d, p1c, p2a) 11.3.1 configuration of input port the following paragraphs (1) and (2) show the configuration of the input port. (1) p0d (p0d3, p0d2, p0d1, p0d0) (2) p1c (p1c3, p1c2, p1c1, p1c0) p2a (p2a2, p2a1, p2a0) v dd write instruction read instruction port register (1 bit) p0dpld flag high-on resistance to a/d converter v dd to frequency counter write instruction read instruction port register (1 bit)
m pd17933, 17934 94 11.3.2 using input port the input data is read by executing a read instruction (such as skt) to the port register corresponding to the port pin. 1 is read from the port register when a high level is input to the corresponding port pin; when a low level is input to the port pin, 0 is read from the register. nothing is affected even if a write instruction (such as mov) is executed to the port register. p0d has a pull-down resistor that can be connected or disconnected by software in 1-bit units. the pull-down resistor is connected when 0 is written to the corresponding bit of the port 0d pull-down resistor selection register. when 1 is written to the corresponding bit of this register, the pull-down resistor is disconnected. 11.3.3 port 0d pull-down resistor selection register the port 0d pull-down resistor selection register specifies whether a pull-down resistor is connected to p0d3 through p0d0 pins. the configuration and function of this register are illustrated below. ? port 0d pull-down resistor selection register name flag symbol b 3 p 0 d p l d 3 b 2 p 0 d p l d 2 b 1 p 0 d p l d 1 b 0 p 0 d p l d 0 address (bank15) 6ah read/write r/w port 0d pull-down resistor selection reset by reset pin wdt&sp reset clock stop 0 1 connects pull-down resistor to p0d0 pin disconnects pull-down resistor from p0d0 pin selects pull-down resistor of p0d0 pin retained connects pull-down resistor to p0d1 pin disconnects pull-down resistor from p0d1 pin selects pull-down resistor of p0d1 pin 0 1 connects pull-down resistor to p0d2 pin disconnects pull-down resistor from p0d2 pin selects pull-down resistor of p0d2 pin 0 1 connects pull-down resistor to p0d3 pin disconnects pull-down resistor from p0d3 pin selects pull-down resistor of p0d3 pin 0 1 0 0 0 0 0 0 0 0 at reset
95 m pd17933, 17934 11.3.4 status of input port at reset (1) at reset by reset pin all the input ports are set in the input mode. all the pull-down resistors of p0d are connected. (2) at wdt&sp reset all the input ports are set in the input mode. all the pull-down resistors of p0d are connected. (3) on execution of clock stop instruction all the input ports are set in the input mode. the pull-down resistors of p0d retain the previous status. (4) in halt status the previous status is retained.
m pd17933, 17934 96 11.4.2 using output port the output port outputs the contents of the output latch to each pin. the output data is set by executing a write instruction (such as mov) to the port register corresponding to the port pin. write 1 to the port register to output a high level to the port pin; write 0 to output a low level. however, because p0a is an n-ch open-drain output port, it is floated when it outputs a high level. therefore, an external pull-up resistor must be connected to this port. if a read instruction (such as skt) is executed to the port register, the contents of the output latch are read. 11.4.3 status of output port at reset (1) at reset by reset pin the contents of the output latch are output. the contents of the output latch are reset to 0. 11.4 general-purpose output port (p0a, p0c) 11.4.1 configuration of output port the configuration of the output port is shown below. (1) p0a (p0a1, p0a0) (2) p0c (p0c3, p0c2, p0c1, p0c0) output latch read instruction port register (1 bit) write instruction output latch read instruction port register (1 bit) write instruction v dd
97 m pd17933, 17934 (2) at wdt&sp reset the contents of the output latch are output. the contents of the output latch are reset to 0. (3) on execution of clock stop instruction the contents of the output latch are output. the contents of the output latch are retained. (4) in halt status the contents of the output latch are output. the contents of the output latch are retained.
m pd17933, 17934 98 12. interrupt 12.1 outline of interrupt block figure 12-1 outlines the interrupt block. as shown in the figure, the interrupt block temporarily stops the currently executed program and branches execution to a vector address in response to an interrupt request output by a peripheral hardware unit. the interrupt block consists of an interrupt request servicing block corresponding to each peripheral hardware unit, interrupt enable flip-flop that enables all interrupts, stack pointer that is controlled when an interrupt is accepted, address stack registers, program counter, and interrupt stack. the interrupt control block of each peripheral hardware unit consists of an interrupt request flag (irq ) that detects the corresponding interrupt request, interrupt enable flag (ip ) that enables the interrupt, and vector address generator (vag) that specifies a vector address when the interrupt is accepted. the m pd17934 has the following three types of maskable interrupts. ? int interrupts ? timer 0 and basic interval timer 1 interrupts ? serial interface 1 interrupts when an interrupt is accepted, execution branches to a predetermined address, and the interrupt is serviced.
99 m pd17933, 17934 figure 12-1. outline of interrupt block serial interface 1 ipsio1 flag basic timer 1 ipbtm1 flag timer 0 iptm0 flag int pin ip flag program counter address stack registers stack pointer interrupt stack pointer interrupt control block interrupt enable flip-flop di, ei instruction irqsio1 flag irqbtm1 flag irqtm0 flag ir flag vector address generator 01h vector address generator 02h vector address generator 03h vector address generator 04h system registers
m pd17933, 17934 100 12.2 interrupt control block an interrupt control block is provided for each peripheral hardware unit. this block detects issuance of an interrupt request, enables the interrupt, and generates a vector address when the interrupt is accepted. 12.2.1 configuration and function of interrupt request flag (irq ) each interrupt request flag is set to 1 when an interrupt request is issued by the corresponding peripheral hardware unit, and is reset to 0 when the interrupt is accepted. writing the interrupt request flag to 1 directly is equivalent to issuance of the interrupt request. by detecting the interrupt request flag when an interrupt is not enabled, issuance status of each interrupt request can be detected. once the interrupt request flag has been set, it is not reset until the corresponding interrupt is accepted, or until 0 is written to the flag via a window register. even if two or more interrupt requests are issued at the same time, the interrupt request flag corresponding to the interrupt that has not been accepted is not reset. figures 12-2 through 12-15 show the configuration and function of the respective interrupt request registers. figure 12-2. configuration of serial interface 1 interrupt request register name flag symbol b 3 0 b 2 0 b 1 0 b 0 i r q s i o 1 address (bank15) 3ch read/write r/w serial interface 1 interrupt request reset by reset pin wdt&sp reset clock stop 0 1 interrupt request not issued interrupt request issued indicates interrupt request issuance status of serial interface 1 fixed to ? 0 0 r 0 0 0 r: retained at reset
101 m pd17933, 17934 figure 12-3. configuration of basic timer 1 interrupt request register name flag symbol b 3 0 b 2 0 b 1 0 b 0 i r q b t m 1 address (bank15) 3dh read/write r/w basic timer 1 interrupt request reset by reset pin wdt&sp reset clock stop 0 1 interrupt request not issued interrupt request issued indicates interrupt request issuance status of timer 2 fixed to ? 0 0 r 0 0 0 r: retained at reset
m pd17933, 17934 102 figure 12-4. configuration of timer 0 interrupt request register name flag symbol b 3 0 b 2 0 b 1 0 b 0 i r q t m 0 address (bank15) 3eh read/write r/w timer 0 interrupt request reset by reset pin wdt&sp reset clock stop 0 1 interrupt request not issued interrupt request issued indicates interrupt request issuance status of timer 0 fixed to ? 0 0 r 0 0 0 r: retained at reset
103 m pd17933, 17934 figure 12-5. configuration of int pin interrupt request register name flag symbol b 3 i n t 0 b 2 0 b 1 0 b 0 i r q 0 address (bank15) 3fh read/write r/w int pin interrupt request reset by reset pin wdt&sp reset clock stop 0 1 interrupt request not issued interrupt request issued indicates interrupt request issuance status of int pin fixed to ? low level is input high level is input detects status of int pin 0 1 0 0 r 0 0 u u u u: undefined, r: retained at reset
m pd17933, 17934 104 12.2.2 function and configuration of interrupt request flag (ip ) each interrupt request flag enables the interrupt of the corresponding peripheral hardware unit. in order for an interrupt to be accepted, all the following conditions must be satisfied. ? the interrupt must be enabled by the corresponding interrupt request flag. ? the interrupt request must be issued by the corresponding interrupt request flag. ? the ei instruction (which enables all interrupts) must be executed. the interrupt enable flags are located on the interrupt enable register on the register file. figures 12-6 shows the configuration of each interrupt enable register. figure 12-6. configuration of interrupt enable register name flag symbol b 3 i p s i o 1 b 2 i p b t m 1 b 1 i p t m 0 b 0 i p 0 address (bank15) 2fh read/write r/w interrupt enable reset by reset pin wdt&sp reset clock stop at reset 0 1 0 0 0 0 0 0 0 0 0 1 disables enables enables or disables int pin interrupt disables enables enables or disables timer 0 interrupt disables enables enables or disables basic timer 1 interrupt disables enables enables or disables serial interface 1 interrupt 0 1 0 1 retained
105 m pd17933, 17934 12.2.3 vector address generator (vag) the vector address generator generates a branch address (vector address) of the program memory corresponding to an interrupt source that has been accepted from the corresponding peripheral hardware. table 12-1 shows the vector addresses of the respective interrupt sources. table 12-1. interrupt sources and vector addresses interrupt source vector address int pin 0004h timer 0 0003h basic timer 1 0002h serial interface 1 0001h
m pd17933, 17934 106 12.3 interrupt stack register 12.3.1 configuration and function of interrupt stack register figure 12-7 shows the configuration of the interrupt stack register. the interrupt stack register saves the contents of the following system registers (except the address register (ar)) when an interrupt is accepted. ? window register (wr) ? bank register (bank) ? index register (ix) ? general pointer (rp) ? program status word (psword) when an interrupt is accepted and the contents of the above system registers are saved to the interrupt stack, the contents of the above system registers, except the window register, are reset to 0. the interrupt stack can save the contents of the above system registers at up to four levels. therefore, interrupts can be nested up to four levels. the contents of the interrupt stack register are restored to the system registers when the interrupt return (reti) instruction is executed. the contents of the interrupt stack register are undefined at reset by reset pin. the previous contents are retained on execution of the clock stop instruction. figure 12-7. configuration of interrupt stack register window stack wrsk b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 bank stack banksk index stack h ixhsk index stack m ixhsk index stack l ixhsk pointer stack h rphsk pointer stack l rplsk status stack pswsk bit undefined interrupt stack register (intsk) name address 0h 1h 2h 3h 4h 5h intsk1 intsk2 intsk3 intsk4 interrupt stack pointer of system register bit b 2 b 3 b 0 b 1 s y s r s p 2 0s y s r s p 0 s y s r s p 1 undefined
107 m pd17933, 17934 12.3.2 interrupt stack pointer of system register the interrupt stack pointer of the system register detects the nesting level of interrupts. the interrupt stack pointer can be only read and cannot be written. the configuration and function of the interrupt stack pointer are illustrated below. ( ) name flag symbol b 3 0 b 2 s y s r s p 2 b 1 s y s r s p 1 b 0 s y s r s p 0 address 08h read/write r interrupt stack pointer of system registers 01 1 0 0 1 1 use prohibited 4 levels (intsk1) 3 levels (intsk2) 2 levels (intsk3) 1 level (intsk4) 0 level detects level of interrupt stack of system registers fixed to ? 0 1 0 1 0 1 0 0 1 1 0 0 0 0 0 0 1 1 reset by reset pin wdt&sp reset retained at reset clock stop ( ) ( )
m pd17933, 17934 108 12.3.3 interrupt stack operation figure 12-8 shows the operation of the interrupt stack. when nested interrupts exceeding four levels are accepted, since the contents saved first are discarded they therefore must be saved by the program. figure 12-8. operation of interrupt stack (1/2) (a) where interrupt nesting level is 4 or less undefined undefined undefined undefined main undefined undefined undefined undefined main undefined undefined undefined a main undefined undefined undefined a main undefined undefined b a main undefined undefined main routine interrupt a interrupt b reti reti
109 m pd17933, 17934 figure 12-8. operation of interrupt stack (2/2) (b) where interrupt nesting level is 5 or more caution the system is reset when an interrupt of level 5 is accepted. however, the ispres flag, which resets the non-maskable interrupt if the interrupt stack overflows or underflows, must be set to 1. this flag is 1 after system reset, and can then be written only once. undefined undefined main main undefined undefined undefined a a main undefined undefined b main routine interrupt level 1 interrupt level 2 c b a main d d c b a e interrupt d interrupt e interrupt level 4 interrupt level 5 s y stem reset interrupt a interrupt c
m pd17933, 17934 110 12.4 stack pointer, address stack registers, and program counter the address stack registers save a return address when execution returns from an interrupt routine. the stack pointer specifies the address of an address stack register. when an interrupt is accepted, the value of the stack pointer is decremented by one, and the value of the program counter at that time is saved to an address stack register specified by the stack pointer. next, the interrupt routine is executed. when the interrupt return (reti) instruction is executed after that, the contents of an address stack register specified by the stack pointer are restored to the program counter, and the value of the stack pointer is incremented by one. for further information, also refer to 3. address stack (ask) . 12.5 interrupt enable flip-flop (inte) the interrupt enable flip-flop enables or disables the four types of maskable interrupts. when this flip-flop is set, all the interrupts are enabled. when it is reset, all the interrupts are disabled. this flip-flop is set or reset by dedicated instructions ei (to set) and di (to reset). the ei instruction sets this flip-flop when the instruction next to ei is executed, and the di instruction resets the flip-flop while it is being executed. when an interrupt is accepted, this flip-flop is automatically reset. this flip-flop is also reset at power-on reset, at a reset by the reset pin, at a watchdog timer, overflow or underflow of the stack. the flip-flop retains the previous status on execution of the clock stop instruction.
111 m pd17933, 17934 12.6 accepting interrupt 12.6.1 accepting interrupt and priority the following operations are performed before an interrupt is accepted. (1) each peripheral hardware unit outputs an interrupt request signal to the corresponding interrupt request block if a given interrupt condition (for example, input of the falling signal to the int pin) is satisfied. (2) when each interrupt request block accepts an interrupt request signal from the corresponding peripheral hardware unit, it sets the corresponding interrupt request flag (for example, irq0 flag if it is the int pin that has issued the interrupt request) to 1. (3) the interrupt enable flag corresponding to each interrupt request flag (for example, ip0 flag if the interrupt request flag is irq0) is set to 1 when each interrupt request flag is set to 1, and each interrupt request block outputs 1. (4) the signal output by the interrupt request block is ored with the output of the interrupt enable flip-flop, and an interrupt accept signal is output. this interrupt enable flip-flop is set to 1 by the ei instruction, and reset to 0 by the di instruction. if 1 is output by each interrupt request processing block while the interrupt enable flip-flop is set to 1, the interrupt is accepted. as shown in figure 12-1, the output of the interrupt enable flip-flop is input to each interrupt request block via an and circuit when an interrupt is accepted. the signal input to each interrupt request block causes the interrupt request flag corresponding to each interrupt request flag to be reset to 0 and the vector address corresponding to each interrupt to be output. if the interrupt request block outputs 1 at this time, the interrupt accept signal is not transferred to the next stage. if two or more interrupt requests are issued at the same time, therefore, the interrupts are accepted according to the priority shown in table 12-2. unless the interrupt request enable flag is set to 1, the corresponding interrupt is not accepted. therefore, by resetting the interrupt enable flag to 0, the interrupt with a high hardware priority can be disabled. table 12-2. interrupt priority interrupt source priority int pin 1 timer 0 2 basic timer 1 3 serial interface 1 4
m pd17933, 17934 112 12.6.2 timing chart when interrupt is accepted the timing charts in figure 12-9 illustrate the operations performed when an interrupt or interrupts are accepted. figure 12-9 (1) is the timing chart when one interrupt is accepted. (a) in (1) is the timing chart where the interrupt request flag is set to 1 after all the others, and (b) is the timing chart where the interrupt enable flag is set to 1 after all the others. in either case, the interrupt is accepted when the interrupt request flag, interrupt enable-flip flop, and interrupt enable flag all have been set to 1. if the flag or flip-flop that has been set last is set in the first instruction cycle of the movt dbf, @ar instruction or by an instruction that satisfies a given skip condition, the interrupt is accepted in the second instruction cycle of the movt dbf, @ar instruction or after the instruction that is skipped (this instruction is treated as nop) has been executed. the interrupt enable flip-flop is set in the instruction cycle next to that in which the ei instruction is executed. therefore, the interrupt is accepted after the instruction next to the ei instruction has been executed even when the interrupt request flag is set in the execution cycle of the ei instruction. (2) in figure 12-9 is the timing chart where two or more interrupts are used. when two or more interrupts are used, the interrupts are accepted according to the hardware priority if all the interrupt enable flags are set. however, the hardware priority can be changed by setting the interrupt enable flags by the program. instruction cycle shown in figure 12-9 is a special cycle in which the interrupt request flag is reset, a vector address is specified, and the contents of the program counter are saved after an interrupt has been accepted. it takes 53.3 m s, which is equivalent to one instruction execution time, to be completed. for details, refer to 12.7 operations after interrupt has been accepted .
113 m pd17933, 17934 figure 12-9. timing charts when interrupt is accepted (1/3) (1) when one interrupt (e.g., rising of int pin) is used (a) if there is no interrupt mask time by the interrupt flag (ip ) <1> if a normal instruction which is not movt or an instruction that satisfies a skip condition is executed when interrupt is accepted <2> if movt or an instruction that satisfies a skip condition is executed when interrupt is accepted instruction ei mov wr, #0001b poke intpm, wr movt dbf, @ar or skip instruction interrupt cycle inte 53.3 s interrupt enable period int pin interrupt accepted int pin interrupt service int pin irq0 flag ip0 flag 1 instruction cycle m instruction ei mov wr, #0001b poke intpm, wr normal instruction interrupt cycle inte int pin irq0 flag ip0 flag 1 instruction cycle 53.3 s interrupt enable period int pin interrupt accepted int pin interrupt service m
m pd17933, 17934 114 figure 12-9. timing charts when interrupt is accepted (2/3) (b) if interrupt is kept pending by the interrupt enable flag (2) if two or more interrupts (e.g., int pin and basic timer 1) are used (a) hardware priority instruction ei mov wr, #0001b poke intpm, wr interrupt cycle inte int pin irq0 flag ip0 flag int pin interrupt pending period int pin interrupt accepted int pin interrupt service instruction ei mov wr, #0101b poke intpm, wr interrupt cycle inte int pin irq0 flag basic timer 1 int pin interrupt pending period int pin interrupt accepted int pin interrupt service ei interrupt cycle irqbtm1 flag ip0 flag ipbtm1 flag basic timer 1 interrupt pending period basic timer 1 interrupt service basic timer 1 pin interrupt accepted
115 m pd17933, 17934 figure 12-9. timing charts when interrupt is accepted (3/3) (b) software priority instruction ei mov wr, #0100b poke intpm, wr interrupt cycle inte int pin irq0 flag basic timer 1 basic timer 1 interrupt pending period basic timer 1 pin interrupt accepted basic timer 1 pin interrupt service ei interrupt cycle irqbtm1 flag ip0 flag ipbtm1 flag int pin interrupt pending period int pin interrupt service int pin interrupt accepted mov wr, #0101b poke intpm, wr
m pd17933, 17934 116 12.7 operations after interrupt has been accepted when an interrupt is accepted, the following operations are sequentially performed automatically. (1) the interrupt enable flip-flop and the interrupt request flag corresponding to the accepted interrupt request are reset to 0. as a result, the other interrupts are disabled. (2) the contents of the stack pointer are decremented by one. (3) the contents of the program counter are saved to an address stack register specified by the stack pointer. at this time, the contents of the program counter are the program memory address after the address at which the interrupt has been accepted. for example, if a branch instruction is executed when the interrupt has been accepted, the contents of the program counter are the branch destination address. if a subroutine call instruction is executed, the contents of the program counter are the call destination address. if the skip condition of a skip instruction is satisfied, the next instruction is executed as nop and then the interrupt is accepted. consequently, the contents of the program counter are the address after that of the instruction that is skipped. (4) the contents of the system registers (except the address register) are saved to the interrupt stack. (5) the contents of the vector address generator corresponding to the interrupt that has been accepted are transferred to the program counter. in other words, execution branches to the interrupt routine. the operations (1) through (5) above require the time of one special instruction cycle (53.3 m s) in which normal instruction execution is not performed. this instruction cycle is called an interrupt cycle. in other words, the time of one instruction cycle (53.3 m s) is required after an interrupt has been accepted until execution branches to the corresponding vector address. 12.8 returning from interrupt routine the interrupt return (reti) instruction is used to return from an interrupt routine to the processing during which an interrupt was accepted. when the reti instruction is executed, the following operations are sequentially performed automatically. (1) the contents of an address stack register specified by the stack pointer are restored to the program counter. (2) the contents of the interrupt stack are restored to the system registers. (3) the contents of the stack pointer are incremented by one. the operations (1) through (3) above require one instruction cycle (53.3 m s) in which the reti instruction is executed. the only difference between the reti instruction and the ret and retsk instructions, which are subroutine return instructions, is the restoration of the bank register and index register in step (2) above.
117 m pd17933, 17934 12.9 external interrupts (int pin) 12.9.1 outline of external interrupts figure 12-10 outlines the external interrupts. as shown in the figure, external interrupt requests are issued at the rising or falling edges of signals input to the int pin. whether an interrupt request is issued at the rising or falling edge of an int pin is independently specified by the program. the int pin is a schmitt trigger input pin to prevent malfunctioning due to noise. this pin does not accept a pulse input of less than 100 ns. figure 12-10. outline of external interrupts int int0 flag ieg0 flag edge detection block schmitt trigger irq0 flag interrupt control block
m pd17933, 17934 118 12.9.2 edge detection block the edge detection block specifies the valid edge (rising or falling edge) of an input signal that issues the interrupt request of int pin, by using an interrupt edge selection register. figure 12-11 shows the configuration and function of the interrupt edge selection register. figure 12-11. configuration of interrupt edge selection register name flag symbol b 3 0 b 2 0 b 1 0 b 0 i e g 0 address (bank15) 1fh read/write r/w interrupt edge selection 1 0 1 rising edge falling edge selects input edge to issue interrupt request (int3 pin) fixed to ? reset by reset pin wdt&sp reset clock stop at reset 0 0 r 0 00 r: retained caution the external input delays about 100 ns.
119 m pd17933, 17934 table 12-3. issuance of interrupt request by changing ieg flag changes in ieg0 flag status of int pin issuance of interrupt request status of interrupt request flag 1 ? 0 low level not issued retains previous status (falling) (rising) high level issued set to 1 0 ? 1 low level issued set to 1 (rising) (falling) high level not issued retains previous status 12.9.3 interrupt control block the signal levels that are input to the int pin can be detected by using the int0 flag. because int0 flag is reset independently of interrupts, when the interrupt function is not used the int pin can be used as a 1-bit input port. if the interrupts are not enabled, these ports can be used as general-purpose port pins whose rising or falling edge can be detected by reading the corresponding interrupt request flags. at this time, however, the interrupt request flags are not automatically reset and must be reset by the program. for further information, also refer to 12.2.1 configuration and function of interrupt request flag (irq ) . 12.10 internal interrupts the following three internal interrupts are available. ? timer 0 ? basic timer 1 ? serial interface 1 12.10.1 timer 0 and basic timer 1 interrupts interrupt requests are issued at fixed intervals. for details, refer to 13. timer . 12.10.2 serial interface 1 interrupts interrupt requests can be issued at the end of a serial output or serial input operation. for details, refer to 15. serial interface .
m pd17933, 17934 120 13. timers timers are used to manage the program execution time. 13.1 outline of timers figure 13-1 outlines the timers. the following three timers are available. ? basic timer 0, 1 ? timer 0 basic timer 0 and 1 detect the status of a flip-flop that is set at fixed time intervals in software. timer 0 is a modulo timer and can use interrupts. the clock of each timer is created by dividing the system clock (75 khz). figure 13-1. outline of timers (1) basic timer 0 (2) basic timer 0 clock selection 75 khz btm0cy flag flip-flop clock selection 75 khz interrupt control (3) timer 0 clock selection 4.5 mhz start/stop 8-bit counter interrupt control coincidence detection modulo register tm0 tm1
121 m pd17933, 17934 13.2 basic timer 0 13.2.1 outline of basic timer 0 figure 13-2 outlines basic timer 0. basic timer 0 is used as a timer by detecting in software the btm0cy flag that is set at fixed intervals (125 ms). if the btm0cy flag is read first after reset by reset pin, 1 is always read. after that, the flag is set to 0 at 125 ms intervals. figure 13-2. outline of basic timer 0 remark btm0cy (bit 0 of basic timer 0 carry register: refer to figure 13-3 ) detects the status of the flip- flop. divider 75 khz btm0cy flag flip-flop 125 ms 8 hz
m pd17933, 17934 122 13.2.2 flip-flop and btm0cy flag the flip-flop is set at fixed intervals (125 ms) and its status is detected by the btm0cy flag of the basic timer 0 carry register. when the btm0cy flag is read, it is reset to 0 (read & reset). the btm0cy flag is always set to 1 at reset by reset pin instruction. figure 13-3 shows the configuration of the basic timer 0 carry register. figure 13-3. configuration of basic timer 0 carry register name flag symbol b 3 0 b 2 0 b 1 0 b 0 b t m 0 c y address (bank15) 17h read/write r & reset basic timer 0 carry reset by reset pin wdt&sp reset r: retained clock stop at reset 0 1 1 r r flip-flop is not set flip-flop is set fixed to ? detects status of flip-flop 000
123 m pd17933, 17934 13.2.3 example of using basic timer 0 an example of a program using basic timer 0 is shown below. this program executes processing a every 1 second. example loop: skt1 btm0cy ; branches to next if btm0cy flag is 0 br next add m1, #1 ; adds 1 to m1 ske m1, #08h ; executes processing a if m1 is 8 (1 second has elapsed) br next mov m1, #0 processing a next: processing b ; executes processing b and branches to loop br loop
m pd17933, 17934 124 13.2.4 errors of basic timer 0 errors of basic timer 0 include an error due to the detection time of the btm0cy flag. error due to detection time of btm0cy flag the time to detect the btm0cy flag must be shorter than the time at which the btm0cy flag is set. where the time interval at which the btm0cy flag is detected is t check and the time interval at which the flag is set is t set (125 ms), t check and t set must relate as follows. t check < t set at this time, the error of the timer when the btm0cy flag is detected is as follows, as shown in figure 13-4. 0 < error < t set figure 13-4. error of basic timer 0 due to detection time of btm0cy flag as shown in figure 13-4, the timer is updated because btm0cy flag is 1 when it is detected in step <2>. when the flag is detected next in step <3>, it is 0. therefore, the timer is not updated until the flag is detected again in <4>. this means that the timer is extended by the time of t check3 . h l btm0cy flag setting pulse t set t check1 skt1 btm0cy <1> skt1 btm0cy <2> skt1 btm0cy <3> skt1 btm0cy <4> t check2 t check3 1 0 btm0cy flag
125 m pd17933, 17934 13.3 basic timer 1 13.3.1 general figure 13-5 outlines the basic timer 1. the basic timer 1 issues an interrupt request at fixed time interval and sets the irqbtm1 flag to 1. the time interval of the irqbtm1 flag is set by the btm1ck0 flag of the basic timer 1 clock select register. figure 13-6 shows the configuration of the basic timer 1 clock select register. the interrupt generated by the basic timer 1 is accepted when the irqbtm1 flag is set, if the ei instruction has been issued and the ipbtm1 flag has been set (refer to 12. interrupt ). figure 13-5. outline of basic timer 1 remark btm1ck0 (bit 1 of interrupt edge select register. refer to figure 13-6 ) set the time interval at which the irqbtm1 flag is set. selector divider btm1ck0 flag internal signal 75 khz (fixed) irqbtm1 set signal 32 ms (31.25 hz) 8 ms (125 hz)
m pd17933, 17934 126 13.3.2 clock selection block the clock selection block divides the system clock (75 khz) and sets the time interval at which the irqbtm1 flag is to be set, by using the btm1ck0 flags. figure 13-6 shows the configuration of the basic timer 0 clock selection register. figure 13-6. configuration of basic timer 1 clock selection register name flag symbol b 3 0 b 2 0 b 1 0 b 0 b t m 1 c k 0 address (bank15) 18h read/write r/w basic timer 1 clock selection reset by reset pin wdt&sp reset clock stop at reset 0 1 0 0 r 32 ms (31.25 hz) 8 ms (125 hz) fixed to ? sets time interval at which irqbtm1 flag is set 000 r : retained
127 m pd17933, 17934 13.3.3 application example of basic timer 1 a program example is shown below. example m1 mem 0.10h ; 80-ms counter btimer1 dat 0002h ; symbol definition of basic timer 1 interrupt vector address br start ; branches to start org btimer1 ; program address (0002h) add m1, #0001b ; adds 1 to m1 skt1 cy ; tests cy flag br ei_reti ; returns if no carry mov m1, #0110b processing a ei_reti: ei reti start: mov m1, #0110b ; initializes contents of m1 to 6 bank1 set1 btm1ck ; embedded macro ; sets basic timer 1 interrupt pulse to 8 ms set1 ipbtm1 ; enables basic timer 1 interrupt ei ; enables all interrupts loop: bank0 processing b br loop this program executes processing a every 80 ms. the points to be noted in this case are that the di status is automatically set when an interrupt has been accepted, and that the irqbtm1 flag is set to 1 even in the di status. this means that the interrupt is accepted even if execution exits from an interrupt service routine by execution of the reti instruction, if processing a takes longer than 8 ms. consequently, processing b is not executed.
m pd17933, 17934 128 13.3.4 error of basic timer 1 as described in 13.3.3, the interrupt generated by basic timer 1 is accepted each time the basic timer 1 interrupt pulse falls, if the ei instruction has been executed, and if the interrupt has been enabled. therefore, an error of basic timer 1 occurs only when any of the following operations are performed: ? when the first interrupt after basic timer 1 interrupt has been enabled has been accepted ? when the time interval at which the irqbtm1 flag is to be set is changed, i.e., when the first interrupt is accepted after the interrupt pulse has been changed ? when data has been written to the irqbtm1 flag figure 13-7 shows an error in each of the above operations. figure 13-7. error of basic timer 1 (1/2) (a) when interrupt by basic timer 1 is enabled at point <1> in the above figure, the interrupt by basic timer 1 is accepted as soon as the interrupt is enabled. at this time, the error is Ct set . if an interrupt is enabled by the ei instruction at the next point <3>, the interrupt occurs at the falling edge of the basic timer 1 interrupt pulse. at this time, the error is: Ct set < error < 0 h <1> <2> <3> l 1 0 1 0 ei di ei ei interrupt pending set1 ipbtm1 interrupt accepted interrupt accepted interrupt accepted ei t set basic timer 1 interrupt pulse irqbtm1 flag ipbtm1 flag inte ff
129 m pd17933, 17934 figure 13-7. error of basic timer 1 (2/2) (b) when basic timer 1 interrupt pulse is changed even if the basic timer 1 interrupt pulse is changed to b at point <1> in the above figure, the interrupt is accepted at the next point <2> because the basic timer 1 interrupt pulse does not fall. if the basic timer 1 interrupt pulse is changed to a at <3>, the interrupt is immediately accepted because the basic timer 1 interrupt pulse falls. (c) when irqbtm1 flag is manipulated the interrupt is immediately accepted if the irqbtm1 flag is set to 1 at <1>. if clearing the irqbtm1 flag to 0 overlaps with the falling of the basic timer 1 interrupt pulse at <2>, the interrupt is not accepted. h l ei ei ei ei h l h l 1 0 1 0 ei di internal pulse a internal pulse b basic timer 1 interrupt pulse irqbtm1 flag ipbtm1 flag inte ff <1> basic timer 1 interrupt pulse changed <2> interrupt accepted <3> basic timer 1 interrupt pulse changed interrupt accepted interrupt accepted h l basic timer 1 interrupt pulse irqbtm1 flag ipbtm1 flag inte ff ei ei ei 1 0 1 0 ei di <1> set1 irqbtm1 interrupt accepted interrupt accepted interrupt accepted <2> clr1 irqbtm1 interrupt not accepted
m pd17933, 17934 130 13.3.5 notes on using basic timer 1 when creating a program, such as a program for watch, in which processing is always performed at fixed time intervals by using the basic timer 1 after the supply voltage has been once applied (power-on reset), the basic timer 1 interrupt service must be completed in a fixed time. lets take the following example: example m1 mem 0.10h ; 80-ms counter btimer1 dat 0002h ; symbol definition of interrupt vector address of basic timer 1 br start ; branches to start org btimer1 ; program address (0002h) add m1, #0001b ; adds 1 to m1 skt1 cy ; watch processing if carry occurs br ei_reti ; restores if no carry occurs mov m1, #0110b ; <1> processing b ei_reti: ei reti start: mov m1, #0110b ; initializes contetns of m1 to 6 bank1 set1 btm1ck ; embedded macro ; sets time of interrupt by basic timer 1 to 8 ms set1 ipbtm1 ; embedded macro ; enables interrupt by basic timer 1 ei ; enables all interrupts loop: processing a br loop in this example, processing b is executed every 80 ms while processing a is executed.
131 m pd17933, 17934 13.4 timer 0 13.4.1 outline of timer 0 figure 13-8 outlines timer 0. timer 0 counts the basic clock (75, 25, or external clock (tm0, tm1)) with an 8-bit counter, and compares the count value with a value set in advance. figure 13-8. outline of timer 0 remarks 1. tm0ck1 and tm0ck0 (bits 1 and 0 of timer 0 counter clock selection register: refer to figure 13-9 ) set the basic clock frequency. 2. tm0en (bit 3 of timer 0 counter clock selection register: refer to figure 13-9 ) starts or stops timer 0. 3. tm0res (bit 2 of timer 0 counter clock selection register: refer to figure 13-9 ) resets timer 0 counter. clock selection 75 khz start/stop timre 1 counter (tm0c) tm0ck1 flag tm0ck0 flag tm0en flag coincidence detection circuit tm0res flag dbf timer 0 irqtm0 flag interrupt control dbf timer 0 modulo register (tm0m) tm0/p1c0 tm1/p1c1
m pd17933, 17934 132 13.4.2 clock selection and start/stop control blocks the clock selection block selects a basic clock to operate timer 0 counter. four types of basic clocks can be selected by using the tm0ck1 and tm0ck0 flags. the start/stop block starts or stops the basic clock input to timer 0 by using the tm0en flag. figure 13-9 shows the configuration and function of each flag. 13.4.3 count block the count block counts the basic clock with timer 0 counter, reads the count value, and issues an interrupt request when its count value coincides with the value of the timer 0 modulo register. the timer 0 counter can be reset by the tm0res flag. the timer 0 counter is automatically reset when its value coincides with the value of the timer 0 modulo register. the value of the timer 0 counter can be read via data buffer. data can be written to the value of the timer 0 modulo register via data buffer. figure 13-9 shows the configuration of timer 0 counter clock selection register. figure 13-10 shows the configuration of the timer 0 counter. figure 13-11 shows the configuration of the timer 0 modulo register.
133 m pd17933, 17934 figure 13-9. configuration of timer 0 counter clock selection register caution when the tm0res flag is read, 0 is always read. name flag symbol b 3 t m 0 e n b 2 t m 0 r e s b 1 t m 0 c k 1 b 0 t m 0 c k 0 address (bank15) 2bh read/write r/w timer 0 counter clock selection reset by reset pin wdt&sp reset clock stop at reset 0 1 0 1 0 tm0 tm1 75 khz (13.3 s) 25 khz (40 s) sets basic clock of timer 0 counter 00 0 0 1 1 does not change resets counter resets timer 0 counter (valid on writing) 0 1 0 stops starts starts or stops timer 0 0 1 m m
m pd17933, 17934 134 figure 13-10. configuration of timer 0 counter reads count value of timer 0 data buffer dbf3 don't care dbf2 don't care name symbol address bit data dbf1 dbf0 b 3 b 2 b 1 b 0 b 7 b 6 b 5 b 4 timer 0 counter tm0c 1bh reset by reset pin wdt&sp reset clock stop at reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 transfer data valid data 0 x count value 0ffh 8 bits get put must not be executed
135 m pd17933, 17934 figure 13-11. configuration of timer 0 modulo register sets modulo data of timer 0 data buffer dbf3 don't care dbf2 don't care name symbol address bit data dbf1 dbf0 b 3 b 2 b 1 b 0 b 7 b 6 b 5 b 4 timer 0 modulo register tm0m 1ah reset by reset pin wdt&sp reset clock stop at reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 transfer data valid data 0 1 x setting prohibited modulo counter value 0ffh 8 bits get put
m pd17933, 17934 136 13.4.4 example of using timer 0 (1) modulo timer the modulo timer is used for time management by generating timer 0 interrupt at fixed intervals. an example of a program is shown below. this program executes processing b every 400 m s. tm0data dat 0009h ; count data = 10 start: br initial ; reset address ; interrupt vector address nop ; sio1 nop ; btm1 br int_tm0 ; tm0 nop ; int initial: initflg not tm0en, tm0res, tm0ck1, tm0ck0 ; (stop) , (reset) , (basic clock = 40 m s) mov dbf0, #tm0data mov dbf1, #tm0data shr4 and 0fh put tm0, dbf set1 tm0en ; start set1 iptm0 ; enables timer 0 interrupt ei loop: processing a br loop int_tm0: put dbfstk, dbf ; saves data buffer processing b get dbf, dbfstk ei reti ; return end
137 m pd17933, 17934 13.4.5 error of timer 0 timer 0 has an error of up to 1 basic clock in the following cases. (1) on starting/stopping counter the counter is started or stopped by setting the tm0en flag. therefore, an error of 0 to +1 clocks occurs when the tm0en flag is set, and an error of C1 to 0 clocks occurs when the flag is reset. in all, an error of 1 count occurs. (2) on resetting counter operation an error of 0 to +1 clocks occurs when the counter is reset. (3) on selecting basic clock during counter operation an error of 0 to +1 clocks of the newly selected clock occurs.
m pd17933, 17934 138 14. a/d converter 14.1 outline of a/d converter figure 14-1 outlines the a/d converter. the a/d converter compares the analog voltages input to the ad2 through ad0 pins with the internal compare voltage and converts them into 4-bit digital signals by judging the result of the comparison by software. the result of the comparison is detected by the adccmp flag. this converter is of successive approximation type. figure 14-1. outline of a/d converter remarks 1. adcch1 and adcch0 (bits 1 and 0 of a/d converter channel selection register: refer to figure 14-3 ) select pins used for the a/d converter. 2. adccmp (bit 0 of a/d converter mode selection register: refer to figure 14-5 ) detects the result of comparison. 3. adcstrt (bit 1 of a/d converter mode selection register: refer to figure 14-5 ) detects the operating status. p0d3/ad2 p0d2/ad1 p0d1/ad0 adcch1 flag adcch0 flag input selection block compare voltage generation block r-string d/a converter dbf adccmp flag start/stop control block compare block adcstrt flag
139 m pd17933, 17934 14.2 input selection block figure 14-2 shows the configuration of the input selection block. the input selection block selects a pin to be used by using the adcch1 and adcch0 flags. only one pin can be used for the a/d converter. when one of the p0d1/ad0 through p0d3/ad2 pins is selected, the other two pins are forcibly set in the input port mode. the p0d1/ad0 through p0d3/ad2 pins can be connected to a pull-down resistor if so specified by the p0dpl1 through p0dpld3 flags. to use the p0d1/ad0 through p0d3/ad2 pins for the a/d converter, therefore, disconnect their pull-down resistors to correctly detect an external input analog voltage. (for details, refer to 11.3.3 port 0d pull-down resistor selection register. ) figure 14-3 shows the configuration of the a/d converter channel selection register. figure 14-2. configuration of input selection block p0d3/ad2 p0d2/ad1 p0d1/ad0 selector each input port adcch1 adcch0 compare block v adcin
m pd17933, 17934 140 figure 14-3. configuration of a/d converter channel selection register name flag symbol b 3 0 b 2 0 b 1 a d c c h 1 b 0 a d c c h 0 address (bank15) 24h read/write r/w a/d converter channel selection reset by reset pin wdt&sp reset clock stop at reset 0 1 0 1 0 0 a/d converter not used (general-purpose input port) p0d1/ad0 pin p0d2/ad1 pin p0d3/ad2 pin fixed to ? selects pin used for a/d converter 00 0 0 0 1 1 0 0 retained
141 m pd17933, 17934 14.3 compare voltage generation and compare blocks figure 14-4 shows the configuration of the compare voltage generation block and compare block. the compare voltage generation block switches a tap decoder according to the 8-bit data set to the a/d converter reference voltage setting register and generates 256 different of compare voltages v adcref . in other words, this block is an r-string d/a converter. the supply voltage to this r-string d/a converter is the same as the supply voltage v dd of the device. the compare block compares voltage v adcin input from a pin with compare voltage v adcref . comparison by the comparator is performed as soon as data has been written to the adcstrt flag. it takes the a/d converter the time of executing two instructions (106.6 m s) to perform comparison once. the current operating status of the comparator can be checked by reading the content of the adcstrt flag. the result of the comparison is detected by the adccmp flag. figure 14-5 shows the configuration of a/d converter mode selection register. figure 14-4. configuration of compare voltage generation and compare blocks dbf tap decoder 0 1 2 254 255 v dd a/d converter reference voltage setting register (adcr) 1 2 rr r 3 2 r start/stop control block adcstrt flag adccmp flag comparator - + 2 pf 1/2 v dd v adcin v adcref
m pd17933, 17934 142 figure 14-5. configuration of a/d converter mode selection register name flag symbol b 3 0 b 2 0 b 1 a d c s t r t b 0 a d c c m p address (bank15) 25h read/write r/w a/d converter mode selection reset by reset pin wdt&sp reser clock stop r:retained at reset 0 1 0 0 r v adcin < v adcref v adcin > v adcref detects result of comparison by a/d converter 00 end of conversion conversion in progress detects operating status of a/d converter 0 1 0 0 0 fixed to ?
143 m pd17933, 17934 14.4 comparison timing chart the adcstrt flag is reset to 0 two instructions after the adcstrt flag has been set. at this point, the compare result (adccmp flag) can be read. figure 14-6 shows the timing chart. figure 14-6. timing chart of a/d converters compare operation instruction cycle sample & hold adcstrt flag adccmp flag comparison result a/d converter start instruction nop nop adccmp read a/d converter start instruction
m pd17933, 17934 144 14.5 using a/d converter 14.5.1 comparing with one compare voltage an example of a program in this mode is shown below. example to compare input voltage v adcin of ad0 pin with compare voltage v adcref (127.5/256 v dd ), and branch to aaa if v adcin < v adcref , or to bbb if v adcin > v adcref adcr7 flg 0.0eh.3 ; defines each bit of dbf as adcr data setting flag. adcr6 flg 0.0eh.2 adcr5 flg 0.0eh.1 adcr4 flg 0.0eh.0 adcr3 flg 0.0fh.3 adcr2 flg 0.0fh.2 adcr1 flg 0.0fh.1 adcr0 flg 0.0fh.0 bank15 initflg not p0dpld3, not p0dpld2, p0dpld1, not p0dpld0 ; disconnects pull-down resistor of p0d1 pin. bank0 initflg not adcch1, adcch0 ; selects ad0 pin for a/d converter. initflg adcr7, not adcr6, not adcr5, not adcr4 ; initflg not adcr3, not adcr2, not adcr1, not adcr0 ; put adcr, dbf ; sets compare voltage v adcref . set1 adcstrt ; starts a/d conversion. nop ; waits for duration of two instructions. nop ; skt1 adccmp ; judges result of comparison. br aaa br bbb
145 m pd17933, 17934 14.5.2 successive comparison by means of binary search the a/d converter can compare only one compare voltage at a time. consequently, successive comparison must be executed through program in order to convert input voltages into digital signals. if the processing time of the successive comparison program is different depending on the input voltage, it is not desirable because of the relations with the other programs. therefore, the binary search method described in (1) through (3) below is useful. (1) concept of binary search the following figure illustrates the concept of binary search. first, the compare voltage is set to 1/2v dd . if the result of comparison is true (high level), a voltage of 1/4v dd is applied; if the result is false (low level), a voltage of 1/4v dd is subtracted for comparison. similarly, comparison is performed in sequence from 1/8v dd to 1/16v dd . if the result is false after comparison has been executed four times, 1/16v dd is subtracted, and the comparison ends. 11 15/16 14/16 13/16 12/16 11/16 10/16 9/16 8/16 7/16 6/16 5/16 4/16 3/16 2/16 1/16 0/16 l l l l l l l l 15/16 13/16 11/16 9/16 7/16 5/16 3/16 1/16 h l h l h l h l 7/8 5/8 3/8 1/8 h l h l 3/4 1/4 h l 1/2 first 0 second third fourth subtract 1/16 if false compare voltage ( v dd )
m pd17933, 17934 146 (2) flowchart of binary search start initial setting : select pin to be used. (a/d converter reference voltage setting register) = #1000b : set compare voltage to 1/2v dd . adccmp = 1? y n reset adcrfsel3 flag : detect result of comparison and, : if "0", subtract 1/2v dd and, set adcrfsel2 flag : add both "0" and "1" to 1/4v dd and set compare voltage. adccmp = 1? : detect compare voltage and, reset adcrfsel2 flag : if "0", subtract 1/4v dd and, set adcrfsel1 flag : add both "0" and "1" to 1/8v dd and set compare voltage. adccmp = 1? : detect result of comparison and, y n y n reset adcrfsel1 flag : if "0", subtract 1/8v dd and, set adcrfsel0 flag : add both "0" and "1" to 1/16v dd and set compare voltage. adccmp = 1? : detect compare voltage and, reset adcrfsel0 flag : if "0", subtract 1/16v dd and, y n detect content of a/d converter reference voltage setting register end : if "1", conversion ends.
147 m pd17933, 17934 (3) program example of binary search start: bank1 initflg not adcch1, adcch0 ; selects ad0 pin. initflg p0dpld1 ; sets pull-down resistor of ad0 pin off. initflg not adcrfsel3, adcrfsel2, adcrfsel1, adrfsel0 ; sets compare voltage to 7.5/16 v dd . set1 adcstrt ; a/d comparator starts operating. nop ; 2 wait nop ; skf1 adccmp ; detects adccmp. set1 adcrfsel3 ; if 0, adds 7.5/16 v dd and, clr1 adcrfsel2 ; subtracts 3.5/16 v dd . set1 adcstrt ; a/d comparator starts operating. nop ; 2 wait nop ; skf1 adccmp ; detects adccmp. set1 adcrfsel2 ; if 0, adds 3.5/16 v dd and, clr1 adcrfsel1 ; subtracts 1.5/16 v dd . set1 adcstrt ; a/d comparator starts operating. nop ; 2 wait nop ; skf1 adccmp ; detects adccmp. set1 adcrfsel1 ; if 0, adds 1.5/16 v dd and, clr1 adcrfsel0 ; subtracts 0.5/16 v dd . set1 adcstrt ; a/d comparator starts operating. nop ; 2 wait nop ; skf1 adccmp ; detects adccmp. set1 adcrfsel0 ; if 0, adds 0.5/16 v dd . end:
m pd17933, 17934 148 14.6 cautions on using a/d converter 14.6.1 cautions on selecting a/d converter pin when one of the p0d1/ad0 through p0d3/ad2 pins is selected, the other two pins are forcibly set in the input port mode. the p0d1/ad0 through p0d3/ad2 pins can be connected to a pull-down resistor if so specified by the p0dpl1 through p0dpld3 flags in bank 15. to use the p0d1/ad0 through p0d3/ad2 pins for the a/d converter, therefore, disconnect their pull-down resistors to correctly detect an external input analog voltage. 14.7 status at reset 14.7.1 at reset by reset pin all the p0d1/ad0 through p0d3/ad2 pins are set in the general-purpose input port mode. the p0d1 through p0d3 pins are connected with a pull-down resistor. 14.7.2 at wdt&sp reset all the p0d1/ad0 through p0d3/ad2 pins are set in the general-purpose input port mode. the p0d1 through p0d3 pins are connected with a pull-down resistor. 14.7.3 on execution of clock stop instruction the status of the pin selected for the a/d converter is retained as is. the previous status of the pull-down resistor of the p0d1 through p0d3 pins is retained. 14.7.4 in halt status the status of the pin selected for the a/d converter is retained as is. the previous status of the pull-down resistor of the p0d1 through p0d3 pins is retained.
149 m pd17933, 17934 15. serial interface 15.1 general figure 15-1 shows the outline of the serial interface. this serial interface is of two-wire/three-wire serial i/o type. the former type uses sck and so2/si1 pins. the latter uses sck, si1, and so1 pins. figure 15-1. outline of serial interface remarks 1. sio1ck1 and 0 (bits 0 and 1 of serial i/o clock select register. refer to figure 15-2 ) set a shift clock. 2. sio1ts (bit 0 of serial i/o mode select register. refer to figure 15-3 ) starts/stops communi- cation. 3. sio1hiz (bit 1 of serial i/o mode select register. refer to figure 15-3 ) sets the function of the so1/p0b2 pin. 4. sio1mod (bit 3 of serial i/o mode select register. refer to figure 15-3 ) selects i/o of so2/ si1/p0b1 pin. data i/o control block so2/si1/p0b1 so1/p0b2 presettable shift register (sio1sfr) out in sio1hiz flag sio1mod flag clock i/o control block sck/p0b0 sio1ck1, 0 flags wait control block 75 khz sio1ts flag clock counter clock control block irqsio flag wait signal count value 8
m pd17933, 17934 150 15.2 clock input/output control block and data input/output control block the clock input/output control block and data input/output control block select the operation mode of the serial interface (2-wire or 3-wire mode), control the transmit/receive operation, and select a shift clock. the flags that control these blocks are allocated to the serial i/o clock select register and serial i/o mode select register. figure 15-2 shows the configuration and function of the serial i/o clock select register. figure 15-3 shows the configuration and function of the serial i/o mode select register. table 15-1 shows the setting status of each pin by the corresponding control flags. as shown in this table, the input/output setting flag of each pin must be also manipulated in addition to the control flag of the serial interface, to set each pin. the sio1ck1 and 0 flags select the internal clock (master) or external clock (slave) operation. the sio1hiz flag selects whether the so1/p0b2 pin is used as a serial data output pin. the sio1mod flag selects whether the so1/si1/p0b1 pin is used as a serial data input (si1 pin) or serial data output (so2) pin. figure 15-2. configuration of serial i/o clock select register 0 1 0 1 flag symbol b 3 0 b 2 0 b 1 s i o 1 c k 1 b 0 s i o 1 c k 0 name address (bank15) 1ch read/ write r/w sets shift clock of serial interface external clock 12.5 khz 18.75 khz 37.5 khz 0 0 1 1 fixed to 0 serial i/o clock select register internal clock reset by reset pin wdt&sp reset clock stop at reset 0 0 0 0 00 0 0
151 m pd17933, 17934 figure 15-3. configuration of serial i/o mode select register flag symbol b 3 0 b 2 s i o 1 m o d b 1 s i o 1 h i z b 0 s i o 1 t s name address (bank15) 1dh read/ write r/w starts/stops serial communication stops (wait status) starts 0 1 sets function of pdb2/so1 pin general-purpose input/output port serial data output pin 0 1 selects function of p0b1/si1/so2 pin as serial data input (si1) pin as serial data output (so2) pin 0 1 fixed to ? serial i/o mode select register reset by reset pin wdt&sp reset clock stop at reset 0 0 0 0 00 0 0
m pd17933, 17934 152 table 15-1. set status of each pin by control flags notes 1. to set the 3-wire serial i/o mode, be sure to reset sio1mod to 0 and set sio1hiz to 1. 2. to use the 2-wire serial i/o mode, be sure to reset sio1hiz to 0. control flags of serial interface i/o setting flag of each pin communi- cation mode s i o 1 m o d serial i/o select s i o 1 h i z serial interface pin setting s i o 1 c k 1 s i o 1 c k 0 clock setting pin name p 0 b b i o 2 p 0 b b i o 1 set status of pin 3-wire serial i/o note 1 and 2-wire serial i/o note 2 0 0 external clock p0b0/sck 0 during wait: general-purpose input port wait released: external clock input 1 general-purpose output port 0 1 1 1 0 1 internal clock 0 1 general-purpose input port during wait: waits for internal clock output wait released: internal clock output 0 internal clock (reception) p0b1/si1/ so2 during wait: general-purpose input port wait released: serial input general-purpose output port during wait: waits for serial output wait released: serial output 0 1 0 1 1 output (trans- mission) 0 general- purpose i/o p0b2/so1 general-purpose input port general-purpose output port 1 serial output during wait: waits for serial output wait released: serial output p 0 b b i o 0 0 1 0 1
153 m pd17933, 17934 15.2.1 setting 2-/3-wire mode the serial interface uses two pins in the two-wire mode: sck/p0b0 and so2/si1/p0b1. the sck/p0b0 pin is used as a shift clock input/output pin, and the so2/si1/p0b1 pin is used as a serial data input/output pin. the so1/p0b2 pin is not used for the serial interface and is set in the general-purpose output port mode by the sio1hiz flag. in this way, the serial interface operates in the two-wire mode. in the three-wire mode, three pins, sck/p0b0, so1/p0b2, and so2/si1/p0b1 are used. the sck/p0b0 is used as a shift clock input/output pin, the so1/p0b2 pin is used as a serial data output pin, and the so2/si1/p0b1 pin is used as a serial data input pin. unlike in the two-wire mode, the so1/p0b2 pin is used as a serial data output pin according to the setting of the sio1hiz flag. the so2/si1/p0b1 pin is used as a serial data input pin according to the setting of the sio1mod flag. in this way, the serial interface operates in the three-wire mode. 15.2.2 selecting data input/output using 2-wire serial interface in the two-wire mode, the so2/si1/p0b1 pin is used as an input/output pin for serial data. whether the so2/si1/p0b1 pin is used as a serial data input pin (si1 pin) or serial data output pin (so2 pin) is specified by the sio1mod flag (refer to figure 15-3 configuration of serial i/o mode select register ). 15.3 clock control block the clock control block generates a clock when the internal clock is used (master operation), and controls clock output timing. the frequency f sc of the internal clock is set by the sio1ck0 and sio1ck1 flags of the serial i/o clock select register. figure 15-2 shows the configuration and function of the serial i/o clock select register. for the clock generation timing, refer to 15.7 operation of serial interface . 15.4 clock counter the clock counter counts the shift clock output or input from the shift clock pin (sck/p0b0 pin). because the clock counter directly reads the status of the clock pin, it cannot identify whether the clock is an internal clock or an external clock. the contents of the clock counter cannot be directly read by software. for the operation and timing chart of the clock counter, refer to 15.7 operation of serial interface .
m pd17933, 17934 154 15.5 presettable shift register the presettable shift register is an 8-bit shift register that writes serial-out data and reads serial-in data. writing/reading data to/from the presettable shift register is performed by put and get instructions via data buffer. the presettable shift register outputs (transmits) the content of its most significant bit (msb) from the serial data i/o pin in synchronization with the falling edge of the shift clock, and reads data to its least significant bit (lsb) in synchronization with the rising edge of the shift clock. figure 15-4 shows the configuration and function of the presettable shift register. figure 15-4. configuration of presettable shift register note if the put or get instruction is executed during serial communication, the data may be lost. for details, refer to 15.8 notes on setting and reading data . 15.6 wait control block the wait control block performs wait (pause) control of communication. by releasing the wait status by using the sio1ts flag of the serial i/o mode select register, serial communication is started. after the wait status has been released, and communication has been started, the wait status is resumed if shift clock rises at clock counter 8. the communication status can be detected by the sio1ts flag. that is, the communication status can be detected by detecting the status of the sio1ts flag after setting 1 to the sio1ts flag. if 0 is written to the sio1ts flag while the wait status is released, the wait status is set. this is called a forced wait status. for the configuration and function of the serial i/o mode select register, refer to figure 15-3 . setting of serial-out data and reading of serial-in data dbf3 data buffer name b 0 symbol peripheral register d7 d6 d5 d4 d3 d2 d1 m s b l s b b 1 b 2 b 3 b 4 b 5 b 6 b 7 presettable shift register valid data peripheral address sio1sfr 04h d7 d6 d5 d4 d3 d2 d1 d0 d0 serial out serial in 8 get note put note transfer data don't care dbf2 don't care dbf1 dbf0
155 m pd17933, 17934 15.7 serial interface operation the timing of each operation of the serial interface is described below. this timing is applicable to both 2-wire and 3-wire modes. 15.7.1 timing chart figure 15-5 shows a timing chart. figure 15-5. timing chart of serial interface remark <1> initial status (general-purpose input port) <2> start condition satisfied by general-purpose i/o port <3> wait released <4> wait timing <5> general-purpose input port mode set <6> stop condition satisfied by general-purpose i/o port 15.7.2 operation of clock counter the initial value of the clock counter is 0. the value of the clock counter is incremented each time the falling edge of the clock pin has been detected. when the value of the clock counter reaches 8, it is reset to 0 at the next rising edge of the clock pin. after the clock counter has been reset to 0, the serial communication is placed in the wait status. the conditions under which the clock counter is reset are as follows: (1) at power-on reset (2) when clock stop instruction is executed (3) when 0 is written to sio1ts flag (4) if shift clock rises while wait status is released and present value of clock counter is 8 shift clock serial data clock counter sio1ts <1> <2> <3> <4> <5> <6> int 1 23 78 1 d7 la d6 d5 d1 d0 d7 1 02 7 680 3
m pd17933, 17934 156 15.7.3 wait operation and note when the wait status has been released, serial data is output at the next falling edge of the clock (transmission operation), and the wait released status continues until eight clocks are counted. after the eight clocks have been output, make the shift clock pin high and stop the operations of the clock counter and presettable shift register. note that, if data is written to or read from the presettable shift register while the wait status is released and the shift clock pin is high, the correct data is not set. if data is written to the presettable shift register while the wait status is released and the shift clock pin is low, the content of the msb of the data is output to the serial data output pin when the put instruction is executed. if the forced wait status is set while the wait status is released, the wait status is immediately set when 0 is written to the sio1ts flag. 15.7.4 interrupt request issuance timing an interrupt request is issued when eight clocks have been transmitted (received). 15.7.5 shift clock generation timing (1) when wait status is released from initial status the initial status means the point at which the p0b0/sck pin has been made high with the internal clock operation selected. during the wait status, a high level is output to the shift clock pin. the wait status can be released and a clock can be selected at the same time.
157 m pd17933, 17934 figure 15-6. shift clock generation timing of serial interface (1/4) (2) when wait operation is performed (a) when wait status is set at the 8th clock (normal operation) figure 15-6. shift clock generation timing of serial interface (2/4) 1/f sc wait released 13.33 s initialization wait status shift clock (37.5 khz) 1/f sc wait released 13.33 s initialization wait status shift clock (18.75 khz) 1 : 1 1/f sc wait released initialization wait status shift clock (12.5 khz) 2 : 1 26.66 s 1 : 1 m m m 1/f sc shift clock wait status contents of output latch wait released wait wait released status
m pd17933, 17934 158 (b) when forced wait status is set during wait status figure 15-6. shift clock generation timing of serial interface (3/4) (c) when forced wait status is set while wait status is released figure 15-6. shift clock generation timing of serial interface (4/4) (d) when wait status is released while wait status is released the clock output waveform does not change. neither is the counter reset. however, do not change the clock frequency while the wait status is released. forced wait by sio1ts contents of output latch contents of output latch wait period wait period shift clock 1/f sc shift clock wait status contents of output latch wait released forced wait by sio1ts wait released status 1/f sc shift clock wait status contents of output latch wait released forced wait by sio1ts wait released status
159 m pd17933, 17934 15.8 notes on setting and reading data use the put sio1sfr, dbf instruction to set data to the presettable shift register. use the get dbf, sio1sfr instruction to read data. set or read the data in the wait status. while the wait status is released, the data may not be correctly set or read depending on the status of the shift clock pin. the following table describes the points to be noted in setting and reading data. table 15-2. data read and write operations of presettable shift register and notes status on execution status of shift clock pin operation of presettable shift register of put/get read (get) normal read normal write content of msb is output as data at falling edge of shift clock ? floating with external after wait status is released next (transmission operation). clock ? value of output latch write (put) with internal clock. normally, used with high level low level normal read read (get) high level cannot be read normally. contents of sio1sfr are lost. low level cannot be written normally. contents of sio1sfr are lost. normal write wait content of msb is output as data when put instruction is release executed. status clock counter is not reset. write (put) high level wait status clock msb data wait released put sio1sfr, dbf clock msb data put sio1sfr, dbf
m pd17933, 17934 160 15.9 operation mode and operational outline of each blocks tables 15-3 and 15-4 outline the operations of the serial interface. table 15-3. operation in 3-wire serial i/o mode operation mode slave operation (sio1ck1 = sio1ck0 = 0) master operation (sio1ck1 = sio1ck0 = other than 0) item during wait (sio1ts = 0) wait released (sio1ts = 1) during wait (sio1ts = 0) wait released (sio1ts = 1) status of sck/p0b0 ? when p0bbio0 = 0 ? when p0bbio0 = 0 ? when p0bbio0 = 0 ? when p0bbio0 = 0 each pin general-purpose input port external clock input port general-purpose input port general-purpose input port ? when p0bbio0 = 1 ? when p0bbio0 = 1 ? when p0bbio0 = 1 ? when p0bbio0 = 1 general-purpose output general-purpose output waits for internal clock internal clock output port port output si1/so2/p0b1 sio1mod = 0 ? when p0bbio1 = 0 ? when p0bbio1 = 0 ? when p0bbio1 = 0 ? when p0bbio1 = 0 general-purpose input port serial input general-purpose input port serial input ? when p0bbio1 = 1 ? when p0bbio1 = 1 ? when p0bbio1 = 1 ? when p0bbio1 = 1 general-purpose output general-purpose output general-purpose output general-purpose output port port port port so1/p0b2 sio1hiz = 1 waits for serial output serial output waits for serial output serial output program counter incremented at falling edge of sck pin operation of output ? when sio1hiz = 0 presettable not output shift register ? when sio1hiz = 1 shifted from msb and output from so1 pin at falling edge of sck pin input ? when sio1mod = 0 shifted from lsb and status of si1 pin is input at rising edge of sck pin. if si1 pin is set in output mode, however, contents of output latch are input. CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCC
161 m pd17933, 17934 operation mode slave operation (sio1ck1 = sio1ck0 = 0) master operation (sio1ck1 = sio1ck0 = other than 0) item during wait (sio1ts = 0) wait released (sio1ts = 1) during wait (sio1ts = 0) wait released (sio1ts = 1) status of sck/p0b0 ? when p0bbio0 = 0 ? when p0bbio0 = 0 ? when p0bbio0 = 0 ? when p0bbio0 = 0 each pin general-purpose input port external clock input port general-purpose input port general-purpose input port ? when p0bbio0 = 1 ? when p0bbio0 = 1 ? when p0bbio0 = 1 ? when p0bbio0 = 1 general-purpose output general-purpose output waits for internal clock internal clock output port port output si1/so2/p0b1 sio1mod = 0 ? when p0bbio1 = 0 ? when p0bbio1 = 0 ? when p0bbio1 = 0 ? when p0bbio1 = 0 general-purpose input port serial input general-purpose input port serial input ? when p0bbio1 = 1 ? when p0bbio1 = 1 ? when p0bbio1 = 1 ? when p0bbio1 = 1 general-purpose output general-purpose output general-purpose output general-purpose output port port port port sio1mod = 1 waits for serial output serial output regardless of waits for serial output serial output regardless of regardless of p0bbio1 p0bbio1 regardless of p0bbio1 p0bbio1 so1/p0b2 sio1hiz = 0 ? when p0bbio2 = 0 ? when p0bbio2 = 0 ? when p0bbio2 = 0 ? when p0bbio2 = 0 general-purpose input port serial input general-purpose input port serial input ? when p0bbio2 = 1 ? when p0bbio2 = 1 ? when p0bbio2 = 1 ? when p0bbio2 = 1 general-purpose output general-purpose output general-purpose output general-purpose output port port port port sio1mod = 1 waits for serial output serial output regardless of waits for serial output serial output regardless of regardless of p0bbio2 p0bbio2 regardless of p0bbio2 p0bbio2 program counter incremented at falling edge of sck pin operation of output ? when sio1sel = 1 presettable shifted from msb and output from so2 pin at falling edge of sck pin shift register input ? when sio1sel = 0 shifted from lsb and status of si1 pin is input at rising edge of sck pin. if si1 pin is set in output port mode, however, contents of output latch are input. table 15-4. operation in two-wire serial i/o mode CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCC
m pd17933, 17934 162 15.10 status on reset 15.10.1 at reset by reset pin p0b0/sck, p0b1/si1/so2, and p0b2/so1 pins are set in the general-purpose input port mode. the contents of the presettable shift register are undefined. 15.10.2 wdt&sp reset p0b0/sck pin, p0b1/si1/so2, and p0b2/so1 pins are set in the general-purpose input port. the previous contents of the presettable shift register are retained. 15.10.3 at clock stop all the pins hold the current status. the previous contents of the presettable shift register are retained. 15.10.4 in halt status all the pins hold the current status. the internal clock stops output in the status in which the halt instruction is executed. when the external clock is used, the operation continued even if the halt instruction is executed.
163 m pd17933, 17934 16. pll frequency synthesizer the pll (phase locked loop) frequency synthesizer is used to lock a frequency in the mf (medium frequency), hf (high frequency), and vhf (very high frequency) to a constant frequency by means of phase difference comparison. 16.1 outline of pll frequency synthesizer figure 16-1 outlines the pll frequency synthesizer. a pll frequency synthesizer can be configured by connecting an external lowpass filter (lpf) and voltage controlled oscillator (vco). the pll frequency synthesizer divides a signal input from the vcoh or vcol pin by using a programmable divider and outputs a phase difference between this signal and a reference frequency from the eo0 and eo1 pins. figure 16-1. outline of pll frequency synthesizer note external circuit remarks 1. pllmd1 and pllmd0 (bits 1 and 0 of pll mode selection register: refer to figure 16-3 ) selects a division mode of the pll frequency synthesizer. 2. pllscnf (bit 3 of pll mode selection register: refer to figure 16-3 ) selects the least significant bit of the swallow counter. 3. pllrfck2 through pllrfck0 (bits 3 through 0 of pll reference frequency selection register: refer to figure 16-6 ) selects a reference frequency fr of the pll frequency synthesizer. 4. pllul (bit 0 of pll unlock ff register: refer to figure 16-9 ) detects the pll unlock ff status. input select block programmable divider (pd) reference frequency generator 75 khz pllscnf flag dbf pllrfck2 flag pllrfck1 flag pllrfck0 flag pllul flag pllmd1 flag pllmd0 flag vcoh vcol eo1 eo0 phase comparator ( -det) charge pump lowpass filter (lpf) voltage controlled oscillator (vco) unlock ff note note f
164 m pd17933, 17934 16.2 input selection block and programmable divider 16.2.1 configuration and function of input selection block and programmable divider figure 16-2 shows the configuration of the input selection block and programmable divider. the input selection block selects an input pin and division mode of the pll frequency synthesizer. the vcoh or vcol pin can be selected as the input pin. the voltage on the selected pin is at the intermediate level (approx. 1/2 v dd ). the pin not selected is internally pulled down. because these pins are connected to an internal ac amplifier, cut the dc component of the input signal by connecting a capacitor in series to the pin. direct division mode and pulse swallow mode can be selected as division modes. the programmable divider divides the frequency of the input signal according to the value set to the swallow counter and programmable counter. the pin and division mode to be used are selected by the pll mode selection register. figure 16-3 shows the configuration of the pll mode selection register. the value of the programmable divider is set by using the pll data register via data buffer. figure 16-2. configuration of input selection block and programmable divider note pllscnf flag pllmd1 flag pllmd0 flag vcoh vcol pll disable signal 2- modulus prescaler 1/32, 1/33 programmable counter 12 bits f n -det swallow counter 5 bits 4 16 12 dbf pll data register 12 bits 4 bits r f note f to
165 m pd17933, 17934 figure 16-3. configuration of pll mode selection register 16.2.2 outline of each division mode (1) direct division mode (mf) in this mode, the vcol pin is used. the vcoh pin is pulled down. in this mode, only the programmable counter is used for frequency division. (2) pulse swallow mode (hf) in this mode, the vcol pin is used. the vcoh pin is pulled down. in this mode, the swallow counter and programmable counter are used for frequency division. name flag symbol b 3 p l l s c n f b 2 0 b 1 p l l m d 1 b 0 p l l m d 0 address (bank15) 10h read/write r/w pll mode selection reset by reset pin wdt&sp reset clock stop at reset 0 1 0 1 0 0 0 disables vcol and vcoh pins direct division (vcol pin, mf mode) pulse swallow (vcoh pin, vhf mode) pulse swallow (vcol pin, hf mode) selects division mode of pll frequency synthesizer u u r u: undefined r: retained 0 0 0 1 1 fixed to ? 0 0 0 clears least significant bit to 0 sets least significant bit to 1 selects least significant bit of swallow counter 0 1
166 m pd17933, 17934 (3) pulse swallow mode (vhf) in this mode, the vcoh pin is used. the vcol pin is pulled down. in this mode, the swallow counter and programmable counter are used for frequency division. (4) vcol and vcoh pin disabled in this mode, only the vcol and vcoh pins are internally pulled down, but the other blocks operate. 16.2.3 programmable divider and pll data register the programmable divider consists of a 5-bit swallow counter and a 12-bit programmable counter. each counter is a 17-bit binary down counter. the programmable counter is allocated to the high-order 12 bits of the pll data register, and the swallow counter is allocated to the low-order 4 bits. data are set to these counters via data buffer. the least significant bit of the swallow counter sets data to the pllscnf flag of the control register. the value by which the input signal frequency is to be divided is called n value. for how to set a division value (n value) in each division mode, refer to 16.6 using pll frequency synthesizer . (1) pll data register and data buffer figure 16-4 shows the relationships between the pll data register and data buffer. in the direct division mode, the high-order 12 bits of the pll data register are valid, and all 17 bits of the register are valid in the pulse swallow mode. in the direct division mode, all 12 bits are used as a programmable counter. in the pulse swallow mode, the high-order 12 bits are used as a programmable counter, and the low-order 5 bits are used as a swallow counter. (2) relationship between division value n of programmable divider and divided output frequency the relationship between the value n set to the pll data register and the signal frequency f n divided and output by the programmable divider is as shown below. for details, refer to 16.6 using pll frequency synthesizer . (a) direct division mode (mf) f in = f in n: 12 bits n (b) pulse swallow mode (hf, vhf) f in = f in n: 17 bits n
167 m pd17933, 17934 figure 16-4. setting division value (n value) of pll frequency synthesizer note the value of pllscnf flag is transferred when a write (put) instruction is executed to the pll data register (pllr). therefore, data must be set to the pllscnf flag before executing the write instruction to the pll data register. data buffer dbf3 dbf2 name pll data register symbol pllr peripheral address 42h dbf1 dbf0 b 3 b 2 b 1 b 0 b 3 b 0 b 0 b 1 b 1 b 2 b 2 b 3 b 3 b 4 b 4 b 5 b 5 b 6 b 6 b 7 b 7 b 8 b 8 b 9 b 9 b 10 b 10 b 11 b 11 b 12 b 12 b 13 b 13 b 14 b 14 b 15 b 15 b 16 b 6 b 5 b 4 b 10 b 9 b 8 b 7 b 13 b 12 b 15 b 14 b 11 peripheral register pll n value data (17 bits) direct division mode 0 don't care setting prohibited division value n: n = x setting prohibited division value n: n = x don't care don't care don't care 15 (00fh) 2 12 ? (fffh) pulse swallow mode transfer data valid data sets high-order 16 bits of division value sets least significant bit of division value note name pll mode selection address (bank15) 10h b 3 p l l s c n f p l l m d 1 p l l m d 0 0 b 2 b 1 b 0 register file get put 16 sets division value (n value) of pll frequency synthesizer x 0 1023 (3ffh) 2 17 ? (1ffffh) x don't care 16 (010h) 1024 (400h)
168 m pd17933, 17934 16.3 reference frequency generator figure 16-5 shows the configuration of the reference frequency generator. the reference frequency generator generates the reference frequency fr of the pll frequency synthesizer by dividing the 75 khz output of a crystal oscillator. six frequencies can be selected as reference frequency fr: 1, 3, 5, 6.25, 12.5, and 25 khz. the reference frequency fr is selected by the pll reference frequency selection register. figure 16-6 shows the configuration and function of the pll reference frequency selection registerion. figure 16-5. configuration of reference frequency generator pllrfck2 flag pllrfck1 flag pllrfck0 flag mux 1 khz 3 khz 5 khz 6.25 khz 12.5 khz off pll disable signal to -det divider 75 khz f 25 khz
169 m pd17933, 17934 figure 16-6. configuration of pll reference frequency selection register remark when the pll frequency synthesizer is disabled by the pll reference frequency selection register, the vcoh and vcol pins are internally pulled down. the eo1 and eo0 pins are floated. name flag symbol b 3 0 b 2 p l l r f c k 2 b 1 p l l r f c k 1 b 0 p l l r f c k 0 address (bank15) 11h read/write r/w pll reference frequency selection reset by reset pin wdt&sp reset clock stop at reset 0 1 0 1 0 1 0 1 1 1 1 1 khz 3 khz 5 khz 6.25 khz 12.5 khz 25 khz pll disable pll disable sets reference frequency f r of pll frequency synthesizer 0 0 0 0 1 1 1 1 1 1 1 0 0 1 1 0 0 1 1 1 1 1 0 0 0 fixed to ?
170 m pd17933, 17934 16.4 phase comparator ( f -det), charge pump, and unlock ff 16.4.1 configuration of phase comparator, charge pump, and unlock ff figure 16-7 shows the configuration of the phase comparator, charge pump, and unlock ff. the phase comparator compares the phase of the divided frequency f n output by the programmable divider with the phase of the reference frequency fr output by the reference frequency generator, and outputs an up (up) or down (dw) request signal. the charge pump outputs the output of the phase comparator from an error out pin (eo1 and eo0 pins). the unlock ff detects the unlock status of the pll frequency synthesizer. 16.4.2 through 16.4.4 describe the operations of the phase comparator, charge pump, and unlock ff. figure 16-7. configuration of phase comparator, charge pump, and unlock ff unlock ff pllul flag up f r f n charge pump eo1 eo0 reference frequency generator programmable divider dw pll disable signal phase comparator ( - det) f
171 m pd17933, 17934 16.4.2 function of phase comparator as shown in figure 16-7, the phase comparator compares the phases of the divided frequency f n output by the programmable divider and the reference frequency fr, and outputs an up or down request signal. if the divided frequency f n is lower than reference frequency fr, the up request signal is output. if f n is higher than fr, the down request signal is output. figure 16-8 shows the relationship between reference frequency fr, divided frequency f n , up request signal, and down request signal. when the pll frequency synthesizer is disabled, neither the up request nor the down request signal is output. the up and down request signals are input to the charge pump and unlock ff, respectively. figure 16-8. relationship between fr, f n , up, and dw (a) if f n lags behind fr (b) if f n leads fr (c) if f n and fr are in phase (d) if f n is lower than fr f r f n up dw f r f n up dw f r f n up dw f r f n up dw
172 m pd17933, 17934 16.4.3 charge pump as shown in figure 16-7, the charge pump outputs the up request and down request signals output by the phase comparator, from the error out pins (eo1 and eo0 pins). therefore, the relationship between the output of the error out pins, divided frequency f n and reference frequency fr is as follows: where reference frequency fr > divided frequency f n : low-level output where reference frequency fr < divided frequency f n : high-level output where reference frequency fr = divided frequency f n : floating 16.4.4 unlock ff as shown in figure 16-7, the unlock ff detects the unlock status of the pll frequency synthesizer from the up request and down request signals of the phase comparator. because either the up request or down request signal is low in the unlock status, the unlock status is detected by this low-level signal. in the unlock status, the unlock ff is set to 1. the unlock ff is set in the cycle of the reference frequency fr selected at that time. when the contents of the pll unlock ff register are read (by the peek instruction), the unlock ff is reset (read & reset). therefore, the unlock ff must be detected in a cycle longer than cycle 1/fr of the reference frequency fr. the status of the unlock ff is detected by the pll unlock ff register. figure 16-9 shows the configuration of the pll unlock ff register. because this register is a read-only register, its contents can be read to the window register by the peek instruction. because the unlock ff is set in a cycle of the reference frequency fr, the contents of the pll unlock ff register are read to the window register in a cycle longer than cycle 1/fr of the reference frequency. the delay time of the up and down request signals of the phase comparator are fixed to 0.8 to 1.0 m s.
173 m pd17933, 17934 figure 16-9. configuration of pll unlock ff register name flag symbol b 3 0 b 2 0 b 1 0 b 0 p l l u l address (bank15) 12h read/write r & reset pll unlock ff reset by reset pin wdt&sp reset u: undefined r: retained clock stop at reset 0 1 u u r unlock ff = 0: pll locked status unlock ff = 1: pll unlocked status fixed to ? detects status of unlock ff 000
174 m pd17933, 17934 16.5 pll disabled status the pll frequency synthesizer stops when pll disabled status is selected by the pll reference frequency register (rf address 11h). table 16-1 shows the operation of each block in the pll disabled status. when the vcol and vcoh pins are disabled by the pll mode selection register, only the vcol and vcoh pins are internally pulled down, and the other blocks operate. at reset by reset pin, the pll frequency synthesizer is disabled. table 16-1. operation of each block under each pll disable condition condition pll reference frequency pll mode selection selection register = 1111b register = 0000b each block (pll disabled) (vcoh and vcol disabled) vcol, vcoh pins internally pulled down internally pulled down programmable divider division stopped operates reference frequency generator output stopped operates phase comparator output stopped operates charge pump error out pins are floated operates. however, usually outputs low level because no signal is input
175 m pd17933, 17934 16.6 using pll frequency synthesizer to control the pll frequency synthesizer, the following data is necessary. (1) division mode : direct division (mf), pulse swallow (hf, vhf) (2) pins used : vcol and vcoh pins (3) reference frequency : fr (4) division value : n 16.6.1 through 16.6.3 below describe how to set pll data in each division mode (mf, hf, and vhf). 16.6.1 direct division mode (mf) (1) selecting division mode select the direct division mode by using the pll mode selection register. (2) pins used the vcol pin is enabled to operate when the direct division mode is selected. (3) selecting reference frequency fr select the reference frequency by using the pll reference frequency selection register. (4) calculation of division value n calculate n as follows: n = f vcol fr f vcol : input frequency of vcol pin fr : reference frequency (5) example of setting pll data how to set data to receive broadcasting in the following mw band is described below. reception frequency : 1422 khz (mw band) reference frequency : 3 khz intermediate frequency : +450 khz division value n is calculated as follows: n = f vcol = 1422 + 450 = 624 (decimal) fr 3 = 270h (hexadecimal) set data to the pll data register, pll mode selection register, and pll reference frequency selection register as follows:
176 m pd17933, 17934 notes 1. pllscnf flag 2. dont care pll data register (pllr) 0 0 1 0 2 0 0 0 0 0 don't care 0 1 1 1 7 pll mode selection register pll reference frequency selection register note 1 note 2 0 0 0 1 3 khz 0 0 1 mf
177 m pd17933, 17934 16.6.2 pulse swallow mode (hf) (1) selecting division mode select the pulse swallow mode by using the pll mode selection register. (2) pins used the vcol pin is enabled to operate when the pulse swallow mode is selected. (3) selecting reference frequency fr select the reference frequency by using the pll reference frequency selection register. (4) calculation of division value n calculate n as follows: n = f vcol fr f vcol : input frequency of vcol pin fr : reference frequency (5) example of setting pll data how to set data to receive broadcasting in the following sw band is described below. reception frequency : 25.50 mhz (sw band) reference frequency : 5 khz intermediate frequency : +450 khz division value n is calculated as follows: n = f vcol = 25500 + 450 = 5190 (decimal) fr 5 = 1446h (hexadecimal) set data to the pll data register, pll mode selection register, and pll reference frequency selection register as follows: caution the division value n is 17 bits long when the pulse swallow mode is selected, and the least significant bit of the swallow counter is the bit 3 of the pll mode selection register (pllscnf). to set 1446h as the division value n, the value to be actually set to the pll data register is 0a23h. note pllscnf flag pll data register (pllr) 0 0 0 0 0 0 1 00 0 1 1 1 0 1 0 pll mode selection register pll reference frequency selection register note 0 0 0 1 0 0 1 1 5 khz hf 6 4 4 1
178 m pd17933, 17934 16.6.3 pulse swallow mode (vhf) (1) selecting division mode select the pulse swallow mode by using the pll mode selection register. (2) pins used the vcoh pin is enabled to operate when the pulse swallow mode is selected. (3) selecting reference frequency fr select the reference frequency by using the pll reference frequency selection register. (4) calculation of division value n calculate n as follows: n = f vcoh fr f vcoh : input frequency of vcoh pin fr : reference frequency (5) example of setting pll data how to set data to receive broadcasting in the following fm band is described below. reception frequency : 98.15 mhz (fm band) reference frequency : 25 khz intermediate frequency : +10.7 mhz division value n is calculated as follows: n = f vcoh = 98.15 + 10.7 = 4354 (decimal) fr 0.025 = 1102h (hexadecimal) set data to the pll data register, pll mode selection register, and pll reference frequency selection register as follows: caution the division value n is 17 bits long when the pulse swallow mode is selected, and the least significant bit of the swallow counter is the bit 3 of the pll mode selection register (pllscnf). to set 1102h as the division value n, the value to be actually set to the pll data register is 0881h. note pllscnf flag pll data register (pllr) 0 0 0 0 1 0 0 0 0 0 0 1 1 0 0 0 pll mode selection register pll reference frequency selection register note 0 0 1 0 25 khz vhf 2 0 1 1 0 1 0 1
179 m pd17933, 17934 note that data must be set to the pllscnf flag before a write (put) instruction is executed to the pll data register (pllr). example set1 pllscnf mov dbf0, #0 mov dbf1, #4 mov dbf2, #4 put pllr, dbf 16.7 status at reset 16.7.1 at reset by reset pin the pll frequency synthesizer is disabled because the pll reference frequency selection register is initialized to 0111b. 16.7.2 at wdt&sp reset the pll frequency synthesizer is disabled because the pll reference frequency selection register is initialized to 0111b. 16.7.3 on execution of clock stop instruction the pll frequency synthesizer is disabled because the pll reference frequency selection register is initialized to 0111b. 16.7.4 in halt status the set status is retained.
180 m pd17933, 17934 17. intermediate frequency (if) counter 17.1 outline of frequency counter figure 17-1 outlines the frequency counter. the if counter is mainly used to count the intermediate frequency (if) output from a tuner for detecting broadcasting stations. the if counter counts the frequency input to the p1c2/amifc or p1c3/fmifc/amifc pin at fixed intervals (1 ms, 4 ms, 8 ms, or open) by using a 16-bit counter. figure 17-1. outline of if counter remarks 1. ifcmd1 and ifcmd0 (bits 3 and 2 of if counter mode selection register: refer to figure 17-3 ) select the if counter function. 2. ifcck1 and ifcck0 (bits 1 and 0 of if counter mode selection register: refer to figure 17-3 ) select the gate time of the if counter. 3. ifcstrt (bit 1 of if counter control register: refer to figure 17-5 ) control starting of the if counter. 4. ifcgostt (bit 0 of if counter gate status detection register: refer to figure 17-6 ) detects opening/ closing the gate of the if counter function. 5. ifcres (bit 0 of if counter control register: refer to figure 17-5 ) reset the count value of the if counter. i/o selection block gate time control block start/stop control block if counter (16 bits) ifcck1 flag ifcck0 falg ifcstrt flag dbf ifcgostt flag ifcres flag ifcmd1 flag ifcmd0 flag p1c2/amifc p1c3/fmifc/amifc
181 m pd17933, 17934 17.2 if counter input selection block and gate time control block figure 17-2 shows the configuration of the if counter input selection block and gate time control block. the if counter selection block selects whether the p1c2/amifc or p1c3/fmifc/amifc pin is used as an if counter function or a general-purpose input port, by using the if counter mode selection register. the gate time control block selects gate time by using the if counter mode selection register when the frequency counter is used as the if counter. figure 17-3 shows the configuration of the if counter mode selection register. figure 17-2. configuration of if counter input selection block and gate time control block 1/2 p1c3/fmifc/amifc p1c2/amifc input port fmifc amifc ifcmd1 flag ifcmd0 flag gate signal generator frequency gate signal to start/stop control block ifcck1 flag ifcck0 flag selector
182 m pd17933, 17934 figure 17-3. configuration of if counter mode selection register name flag symbol b 3 i f c m d 1 b 2 i f c m d 0 b 1 i f c c k 1 b 0 i f c c k 0 address (bank15) 22h read/write r/w if counter mode selection reset by reset pin wdt&sp reset clock stop at reset 0 1 0 1 0 0 0 1 ms 4 ms 8 ms open selects gate time of if counter 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 0 1 if counter off mode (general-purpose input port) amifc pin, amif count mode fmifc pin, fmif count mode, 1/2 division fmifc pin, amif count mode selects function of if counter 0 0 1 1
183 m pd17933, 17934 17.3 start/stop control block and if counter 17.3.1 configuration of start/stop control block and if counter figure 17-4 shows the configuration of the start/stop control block and if counter. the start/stop control block starts the frequency counter or detects the end of counting. the counter is started by the if counter control register. the end of counting is detected by the if counter gate status detection register. figure 17-6 shows the configuration of the if counter control register. figure 17-7 shows the configuration of the if counter gate status detection register. 17.3.2 describes the gate operation when the if counter function is selected. the if counter is a 16-bit binary counter that counts up the input frequency when the if counter function is selected. when the if counter function is selected, the frequency input to a selected pin is counted while the gate is opened by an internal gate signal. the frequency count is counted without alteration in the amif count mode. in the fmif counter mode, however, the frequency input to the pin is halved and counted. when the if counter counts up to ffffh, it remains at ffffh until reset. the count value is read by the if counter data register (ifc) via data buffer. the count value is reset by the if counter control register. figure 17-7 shows the configuration of the if counter data register. figure 17-4. configuration of start/stop control block and if counter start/stop control if counter (16 bits) 16 if counter data register (ifc) dbf ifcstrt flag ifcres flag ifcgostt flag gate signal frequency from gate time selection block 16 res
184 m pd17933, 17934 figure 17-5. configuration of if counter control register name flag symbol b 3 0 b 2 0 b 1 i f c s t r t b 0 i f c r e s address (bank15) 23h read/write w if counter control 0 1 nothing is affected resets counter resets data of if counter nothing is affected resets counter fixed to ? start if counter 0 1 reset by reset pin wdt&sp reset clock stop at reset 0 0 0 0 00 0 0
185 m pd17933, 17934 figure 17-6. configuration of if counter gate status detection register caution do not read the contents of the if counter data register (ifc) to the data buffer while the ifcgostt flag is set to 1. name flag symbol b 3 0 b 2 0 b 1 0 b 0 i f c g o s t t address (bank15) 21h read/write r if counter gate status detection 0 1 detects opening/closing of gate of if counter fixed to 0 reset by reset pin wdt&sp reset clock stop at reset 0 0 0 0 00 close open
186 m pd17933, 17934 17.3.2 operation of gate when if counter function is selected (1) when gate time of 1, 4, or 8 ms is selected the gate is opened for 1, 4, or 8 ms from the rising of the internal 1-khz signal after the ifcstrt flag has been set to 1, as illustrated below. while this gate is open, the frequency input from a selected pin is counted by a 16-bit counter. when the gate is closed, the ifcgostt flag is cleared to 0. the ifcgostt flag is automatically set to 1 when the ifcstrt flag is set. (2) when gate is open if opening of the gate is selected by the ifcck1 and ifcck0 flags, the gate is opened as soon as its opening has been selected, as illustrated below. if the counter is started by using the ifcstrt flag while the gate is open, the gate is closed after undefined time. to open the gate, therefore, do not set the ifcstrt flag to 1. however, the counter can be reset by the ifcres flag. sets ifcck1 = ifcck0 = 1 gate is actually opened at this point. if g ate is opened while ifcgostt fla g is 1, it is closed after undefined time count period gate is closed after undefined time if ifcstrt flag is set during this period h internal 1 khz l open close gate the gate is opened or closed in the following two ways when opening the gate is selected as the gate time. gate is actually opened at this point count period (ifcgostt flag = 1) ifcstrt flag is set ifcgostt flag is set at this point end of counting ifgostt flag is cleared h internal 1 khz 1 ms gate time 4 ms 8 ms l open close
187 m pd17933, 17934 (a) resetting the gate to other than open by using ifcck1 and ifcck0 flags (b) unselect pin used by using ifcmd1 and ifcmd0 flags in this way, the gate remains open, and counting is stopped by disabling input from the pin. 17.3.3 function and operation of 16-bit counter the 16-bit counter counts up the frequency input within selected gate time. the 16-bit counter can be reset by writing 1 to the ifcres flag of the if counter control register. once the 16-bit counter has counted up to ffffh, it remains at ffffh until it is reset. the if counter counts the frequency input to the p1c2/amifc or p1c3/fmifc/amifc pin while the gate is open. note, however, in the fmif count mode input to the p1c3/fmifc/amifc is divided by two and counted. the relationship between count value x (decimal) and input frequencies (f fmifc and f amifc ) is shown below. ? fmifc f fmifc = x 2 (khz) t gate : gate time (1 ms, 4 ms, 8 ms) t gate ? amifc f amifc = x (khz) t gate : gate time (1 ms, 4 ms, 8 ms) t gate the value of the if counter data register is read via data buffer. figure 17-7 shows the configuration and function of the if counter data register. gate open close sets ifcck1 = ifcck0 = 1 count period sets ifcmd1 = ifcmd0 = 0 (general-purpose input port) fmifc and amifc pins are unselected and count signal cannot be input ifcck1 = ifcck0 = 1 count period resetting the gate to other than open by ifcck1 and ifcck0 flags open gate close
188 m pd17933, 17934 figure 17-7. configuration of if counter data register once the if counter data register has counted up to ffffh, it remains at ffffh until the counter is reset. data buffer dbf3 dbf2 name if counter data register symbol ifc peripheral address 43h dbf1 dbf0 b 3 b 2 b 1 b 0 b 6 b 5 b 4 b 10 b 9 b 8 b 7 b 13 b 12 b 15 b 14 b 11 peripheral register 0 transfer data valid data get can be executed put changes nothing 16 count value of if counter x 2 16 ? (ffffh) ? fmif count mode of fmifc pin counts rising edge of signal input to p1c3/fmifc/amifc pin via 1/2 divider ? amif count mode of amifc pin counts rising edge of signal input to p1c2/amifc pin ? amif count mode of fmifc pin counts rising edge of signal input to p1c3/fmifc/amimc pin
189 m pd17933, 17934 17.4 using if counter the following sections 17.4.1 through 17.4.3 describe how to use the hardware of the if counter, a program example, and count error. 17.4.1 using hardware of if counter figure 17-8 shows the block diagram when the p1c2/amifc and p1c3/fmifc/amifc pins. as shown in the figure, the if counter uses an input pin with an ac amplifier, the dc component of the input signal must be cut with a capacitor. when the p1c2/amifc or p1c3/fmifc/amifc pin is selected for the if counter function, switch sw turns on, and the voltage level on each pin reaches about 1/2v dd . if the voltage has not risen to a sufficient intermediate level at this time, the if counter does not operate normally because the ac amplifier is not in the normal operating range. therefore, make sure that a sufficient wait time elapses after each pin has been specified to be used for the if counter until counting is started. figure 17-8. if count function block diagram of each pin to internal counter sw r c fmifc amifc external frequecny
190 m pd17933, 17934 17.4.2 program example of if counter a program example of the if counter is shown below. as shown in this example, make sure that a wait time elapses after an instruction that selects the p1c2/amifc or p1c3/fmifc/amifc pin for the if counter function has been executed until counting is started. this is because, as described in 17.4.1, the internal ac amplifier does not operate normally immediately after a pin has been selected for the if counter. example to count the frequency input to the p1c3/fmifc pin (fmif count mode) (gate time: 8 ms) initflg ifcmd1, not ifcmd0, ifcck1, not ifcck0 ; selects fmifc pin (fmif count mode), and sets gate time to 8 ms wait ; internal ac amplifier stabilization time set1 ifcres ; resets counter set1 ifcstrt ; starts counting loop: skt1 ifcg0stt ; detects opening or closing of gate br read ; branches to read: if gate is closed processing a br loop ; do not read data of if counter with this processing a read: get dbf, ifc ; reads value of if counter data register to data buffer 17.4.3 error of if counter the errors of the if counter include a gate time error and a count error. the following paragraphs (1) and (2) describe each of these errors. (1) gate time error the gate time of the if counter is created by dividing the 75-khz clock. therefore, if the system clock is shifted from 75 khz by +x ppm, the gate time is shifted by Cx ppm. (2) count error the if counter counts frequency by the rising edge of the input signal. if a high level is input to the pin when the gate is open, therefore, one excess pulse is counted. if the gate is closed, however, a count error due to the status of the pin does not occur. therefore, the count error is +1, C0.
191 m pd17933, 17934 17.5 status at reset 17.5.1 at reset by reset pin the p1c2/amifc and p1c3/fmifc/amifc pins are set in the general-purpose input port mode. 17.5.2 at wdt&sp reset the p1c2/amifc and p1c3/fmifc/amifc pins are set in the general-purpose input port mode. 17.5.3 on execution of clock stop instruction the p1c2/amifc and p1c3/fmifc/amifc pins are set in the general-purpose input port mode. 17.5.4 in halt status the p1c2/amifc and p1c3/fmifc/amifc pins retain the status immediately before the halt mode is set.
192 m pd17933, 17934 18. beep 18.1 outlines of beep figure 18-1 outlines beep. beep outputs a clock of 1.5 khz or 3 khz from the beep pin. the output select block selects, by using the beep0sel flag, whether the p0b3/beep pin is used as a general- purpose i/o port pin or beep output pin. the beep0ck0 and beep0ck1 flags of the beep clock select register are used to select whether the output frequency of the p0b3/beep pin is 1.5 khz or 3 khz, or the output level of the beep pin. the clock generation block generates the 1.5-khz or 3-khz clock to be output to the p0b3/beep pin. figure 18-2 shows the configuration and function of the beep clock select register. figure 18-1. outline of beep beep0ck0 flag beep0ck1 flag beep0sel flag output select block 1.5 khz 3 khz clock generation block p0b3/beep
193 m pd17933, 17934 figure 18-2. configuration and function of beep clock select register 0 1 0 1 flag symbol b 3 0 b 1 b e e p 0 c k 1 b 0 b e e p 0 c k 0 name address (bank15) 14h read/ write r/w setting of beep pin (when beep0sel=1) outputs low level outputs high level outputs 1.5 khz clock outputs 3 khz clock 0 0 1 1 fixed to 0 beep clock select register b 2 b e e p 0 s e l selecting general-purpose i/o port and beep uses p0b3/beep pin as general-purpose i/o port uses p0b3/beep pin as beep 0 1 reset by reset pin wdt&sp reset clock stop at reset 0 0 0 0 0 0 0 0 0 0 0 0
194 m pd17933, 17934 18.2 output wave form of beep (1) output wave of f = 1.5 khz and f = 3 khz example program to output 3-khz clock from p0b3/beep pin bank1 ; same as mov bank, #0001b mov 14h, #0011b ; writes 0011b to data memory address 14h ; outputs 3 khz from beep pin (2) maximum time until clock is output from p0b3/beep pin after instruction execution (3) minimum time until clock is output from p0b3/beep pin after instruction execution beep (f = 1.5 khz) 333.3 s 333.3 s beep (f = 3 khz) 133.3 s 200 s mm m m beep (f = 1.5 khz) 325.8 s instruction execution beep (f = 3 khz) 325.8 s instruction execution m m beep (f = 1.5 khz) beep (f = 3 khz) 133.3 s instruction execution 133.3 s instruction execution m m
195 m pd17933, 17934 18.3 status at reset 18.3.1 at reset by reset pin the p0b3/beep pin is set in the general-purpose input port mode. 18.3.2 wdt&sp reset p0b3/beep pin is set in the general-purpose input port mode. 18.3.3 on execution of clock stop instruction the p0b3/beep pin is set in the general-purpose input/output port mode. 18.3.4 in halt status the p0b3/beep output pin retains the previous status.
196 m pd17933, 17934 19. lcd controller/driver the lcd (liquid crystal display) controller/driver can display an lcd of up to 60 dots by a combination of command signal and segment signal outputs. 19.1 outline of lcd controller/driver figure 19-1 outlines the lcd controller/driver. the lcd controller/driver can be used to display up to 60 dots by using a combination of common signal output pins (com0 through com3) and segment signal output pins (lcd0 through lcd19). the drive mode is 1/4 duty, 1/2 bias, the frame frequency is 62.5 hz, and drive voltage is v lcd . among the segment signal output pins, lcd17 through lcd19 can be used as a general-purpose input port. for details of the general-purpose input port, refer to 11.3 general-purpose input port ( p0d, p1c, p2a ). figure 19-1. outline of lcd controller/driver remarks 1. lcden (bit 0 of lcd driver display start register: refer to figure 19-8 ) turns on/off all lcd display. 2. lcd19sel-lcd17sel (bits 2-0 of lcd port select register: refer to figure 19-6 ) segment signal output timing control block common signal output timing control block lcd drive voltage generation block lcd segment register (data memory space) basic clock for timing control lcd0 pin p2a0/lcd17 pin com0 pin com3 pin reg lcd 0 pin reg lcd 1 pin reg lcd 2 pin segment signal/ general input port select block p2a1/lcd18 pin p2a2/lcd19 pin lcd19sel-lcd17sel lcden flag cap lcd 0 pin cap lcd 1 pin cap lcd 2 pin cap lcd 3 pin
197 m pd17933, 17934 19.2 lcd drive voltage generation block the lcd drive voltage generation block generates a voltage to drive the lcd. the m pd17934 supplies the lcd drive voltage from an external doubler circuit. to configure a doubler circuit, connect a capacitor to the cap lcd 0, cap lcd 1, cap lcd 2, cap lcd 3, reg lcd 0, reg lcd 1, and reg lcd 2 pins. figure 19-2 shows an example of configuration of the doubler circuit. to use a voltage of 3.0 v (typ.), connect as shown in figure 19-2. to operate the doubler circuit, the lcden flag of the lcd display start register must be set to 1. unless this flag is set to 1, the lcd drive voltage generation block does not operate. for the lcden flag, refer to 19.5 common signal output and segment signal output timing control blocks . figure 19-2. configuration of doubler circuit remark ( ): pin number note that, because of the configuration of the doubler circuit, the values of the lcd drive voltages (v lcd1 and v lcd0 ) differ if the values of c1, c2, c3, c4, and c5 are changed. reg lcd 2 cap lcd 3 cap lcd 2 reg lcd 1 reg lcd 0 cap lcd 1 c5 c3 c2 c1 to c5 = 0.33 f c4 c1 v lcd0 v lcd1 m cap lcd 0
198 m pd17933, 17934 19.3 lcd segment register the lcd segment register sets dot data to turn on or turn off dots on the lcd. figure 19-3 shows the location in the data memory and configuration of the lcd segment register. because the lcd segment register is located in data memory, it can be controlled by all the data memory manipulation instructions. one nibble of the lcd segment register can set display data of 4 dots (data to turn dots on or off). if the lcd segment register is set to 1 at this time, the lcd display dot is on; the dot goes off if the register is set to 0. figure 19-4 shows the relation between the lcd segment register and lcd display dot. figure 19-3. location on data memory and configuration of lcd segment register column address 0123456789abcdef bank0 dbf row address 0 1 2 3 4 5 6 7 bcdef system register 0 1 2 3 4 5 6 7 lcd segment register (bank 14) address symbol read/write b 3 b 2 b 1 b 0 lcdd19 r/w 5ch lcdd19 r/w 5dh lcdd18 r/w 5eh lcdd17 r/w 5fh lcdd16 r/w 60h lcdd15 r/w 61h lcdd14 r/w 62h lcdd13 r/w 63h lcdd12 r/w 64h lcdd11 r/w 65h lcdd10 r/w 66h lcdd9 r/w 67h lcdd8 r/w 68h lcdd7 r/w 69h lcdd6 r/w 6ah lcdd5 r/w 6bh lcdd4 r/w 6ch lcdd3 r/w 6dh lcdd2 r/w 6eh lcdd1 r/w 6fh lcdd0 r/w bank14 data memory lcd segment register
199 m pd17933, 17934 figure 19-4. relation between lcd segment register and lcd display dot lcd segment register address symbol bit display dot 5ch lcdd19 5dh lcdd18 5eh lcdd17 5fh lcdd16 60h lcdd15 61h lcdd14 62h lcdd13 6eh lcdd1 6fh lcdd0 b 3 a b 2 b b 1 c b 0 d b 3 a b 2 b b 1 c b 0 d b 3 e b 2 f b 1 g b 0 h b 3 a b 2 b b 1 c b 0 d b 3 e b 2 f b 1 g b 0 h b 3 a b 2 b b 1 c b 0 d b 3 e b 2 f b 1 g b 0 h b 3 a b 2 b b 1 c b 0 d b 3 e b 2 f b 1 g b 0 h a b c d a b c d e f g h a b c d e f g h a b c d e f g h a b c d e f g h lcd19/p2a2 pin lcd18/p2a1 pin lcd17/p2a0 pin lcd16 pin lcd15 pin lcd14 pin lcd13 pin lcd1 pin lcd0 pin com3 pin com2 pin com1 pin com0 pin
200 m pd17933, 17934 19.4 segment signal/general-purpose input port select block figure 19-5 shows the configuration of the segment signal/general-purpose input port select block. this block specifies, by using the lcd19sel through lcd17sel flags of the lcd port select register, whether each pin is used as a segment signal output pin or a general-purpose input port pin. when each flag is 1, the corresponding pin is used as a segment signal output pin; when it is 0, the pin is used as a general-purpose input port pin. figure 19-6 shows the configuration of the lcd port select register. figure 19-5. configuration of segment signal/general-purpose port select block note the lcd19/p2a2 pin corresponds to the lcd19sel flag and bit 2 of p2a, the lcd18/p2a1 pin, to the lcd18sel flag and bit 1 of p2a, and the lcd17/p2a0 pin, to the lcd17sel flag and bit 0 of p2a, respectively. from bit 2 of p2a note segment signal/key source signal from output timing control block segment signal port data input 1 0 lcd19/p2a2 lcd19sel flag note lcd17/p2a0
201 m pd17933, 17934 figure 19-6. configuration of lcd port select register name flag symbol b 3 0 b 2 l c d 1 9 s e l b 1 l c d 1 8 s e l b 0 l c d 1 7 s e l address 69h read/ write r/w selects lcd segment signal output pin or general-purpose input port pin uses lcd19/p2a2 pin as general-purpose input port pin. uses lcd19/p2a2 pin as lcd segment pin. 0 1 selects lcd segment signal output pin or general-purpose input port pin uses lcd18/p2a1 pin as general-purpose input port pin. uses lcd18/p2a1 pin as lcd segment pin. 0 1 selects lcd segment signal output pin or general-purpose input port pin uses lcd17/p2a0 pin as general-purpose input port pin. uses lcd17/p2a0 pin as lcd segment pin. 0 1 fixed to "0". lcd port select register at reset reset by reset pin wdt & sp reset 0 0 0 0 0 0 0 clock stop r: retained rrr
202 m pd17933, 17934 19.5 common signal output and segment signal output timing control blocks figure 19-7 shows the common signal output and segment signal output timing control blocks. the common signal output timing control block controls the common signal output timing of the com0 through com3 pins. the segment signal output timing control block controls the segment signal output timing of the lcd0 through lcd19 pins. the common and segment signals are output when the lcden flag of the lcd driver display start register is set to 1. when this flag is reset to 0, all the lcd display dots can be extinguished (refer to figure 19-8 ). when lcd display is not carried out, the com0 through com3 and lcd0 through lcd19 pins output low level. figure 19-7. configuration of common signal output and segment signal output timing control blocks segment signal common signal lcd0 | lcd19 com0 | com3 segment signal output timing control block basic clock for timing control common signal output timing control block lcden flag lcdd0 | lcdd19 b 0 b 1 b 2 b 3
203 m pd17933, 17934 figure 19-8. configuration of lcd driver display start register note bit 3 of the lcd display start register is a test mode area. therefore, do not write 1 to this bit. 19.6 common signal and segment signal output waves figure 19-9 shows an example of the common signal and segment signal output waves. the m pd17934 outputs a signal with a frame frequency of 62.5 hz using a 1/4 duty, 1/2 bias (voltage average method) drive mode. as the common signals, the com0 through com3 pins output three levels of voltages (gnd, v lcd0 , and v lcd1 ) each having a phase difference of 1/8 from the others. in other words, voltages of 1/2v dd are output with the v lcd0 as the reference. this display method is called the 1/2 bias drive method. as the segment signals, the segment signal output pins output voltages of two levels (gnd and v lcd1 ) having a phase corresponding to each display dot. because one segment pin can turn on or off four display dots (a, b, c, and d) as shown in figure 19-9, sixteen phases can be output by combining lighting and extinguishing of each dot. each display dot turnd on when the potential difference between a common signal and a segment signal is v lcd1 . in other words, the duty factor at which each display dot turns on is 1/4. this display method is called the 1/4 duty display method, and the frame frequency is 62.5 hz. name flag symbol b 3 l c d d b c k b 2 0 b 1 0 b 0 l c d e n address (bank15) 40h read/ write r/w sets on/off of all lcd displays display off (all segment and common output pins output low level) display on 0 1 fixed to ? lcd driver display start register remark r: retained reset by reset pin wdt&sp reset clock stop at reset 0 0 0 0 0 0 0 0 0 0 0 0 note
204 m pd17933, 17934 figure 19-9. common signal and segment signal output waveforms com0 pin com1 pin com2 pin com3 pin a b c d each segment signal output pin (lcdn pin) common signal com0 pin com1 pin com2 pin com3 pin 4 ms v lcd1 v lcd0 gnd v lcd1 v lcd0 gnd v lcd1 v lcd0 gnd v lcd1 v lcd0 gnd v lcd1 gnd v lcd1 gnd v lcd1 gnd a, b, c, d = lights lcdn pin a, b, c = lights, d = extinguishes lcdn pin segment signal (example) 1 frame (16 ms) a, b, c, d = extinguishes lcdn pin
205 m pd17933, 17934 19.7 using lcd controller/driver figure 19-10 shows an example of wiring of an lcd panel using the pins lcd0 through lcd14. an example of a program that lights the 7 segments connected to lcd0 and lcd1 pins shown in figure 19-10 is given below. example pmn0 mem 0.01h ; preset number storage area ch flg lcdd0.3 ; defines symbol with high-order 1 bit of lcd0 register for ch display lcddata: ; lcd segment table data dw 0000000000000000b ; blank dw 0000000000000110b ; 1 dw 0000000010110101b ; 2 dw 0000000010100111b ; 3 dw 0000000001100110b ; 4 dw 0000000011100011b ; 5 dw 00000000 11110011b ; 6 dw 0000000010000110b ; 7 dw 00000000 11110111b ; 8 dw 0000000011100111b ; 9 mov ar0, #.dl.lcddata shr 12 and 0fh mov ar1, #.dl.lcddata shr 8 and 0fh mov ar2, #.dl.lcddata shr 4 and 0fh mov ar3, #.dl.lcddata and 0fh ld dbf0, ar0 ld dbf1, ar1 ld dbf2, ar2 ld dbf3, ar3 add dbf0, pmn0 addc dbf1, #0 addc dbf2, #0 addc dbf3, #0 st ar0, dbf0 st ar1, dbf1 st ar2, dbf2 st ar3, dbf3 movt dbf, @ar ; table reference instruction bank1 st lcdd0, dbf0 st lcdd1, dbf1 set1 ch set1 lcden ; lcd on
206 m pd17933, 17934 figure 19-10. example of wiring of lcd panel (when lcd0-lcd14 pins are used) 1 b 1 f 1 c 1 e 1a 1g 1d 2 b 2 f 2 c 2 e 2a 2g 2d 3 b 3 f 3 c 3 e 3a 3g 3d 4 b 4 f 4 c 4 e 4a 4g 4d 5a 5 b 5 f 5 c 5 e 5g 5d fm mw sw lw abcd e f g am pm mhz khz ch lcd0 lcd1 lcd2 lcd3 lcd4 lcd5 lcd6 lcd7 lcd8 lcd9 lcd10 lcd11 lcd12 lcd13 lcd14 com0 com1 com2 com3 segment pin common l c d 14 l c d 13 l c d 12 l c d 11 l c d 10 l c d 9 l c d 8 l c d 7 l c d 6 l c d 5 l c d 4 l c d 3 l c d 2 l c d 1 l c d 0 com3 com2 com1 com0 fm mw sw lw b a 1a 1f 1g 1e 1b 1c 1d 2a 2f 2g 2e 2b 2c 2d 3a 3f 3g 3e c 3b 3c 3d 4a 4f 4g 4e d 4b 4c 4d e f g am pm mhz khz 5a 5f 5g 5e ch 5b 5c 5d correspondence of segment and common pins, and lcd panel display (when lcd0-lcd14 pins are used) ?
207 m pd17933, 17934 19.8 status at reset 19.8.1 at reset by reset pin the lcd0 through lcd16 pins output a low level. the lcd17/p2a0 through lcd19/p2a2 pins are set in the general purpose input port. the com0 through com3 pins also output a low level. therefore, the lcd display is off. the contents of the lcd segment register are undefined. 19.8.2 wdt&sp reset the lcd0 through lcd16 pins output a low level. the lcd17/p2a0 through lcd19/p2a2 pins are set in the general-purpose input port. the com0 through com3 pins output a low level. therefore, the lcd display is off. the contents of the lcd segment register are undefined. 19.8.3 on execution of clock stop instruction the lcd0 through lcd16 pins output a low level. the lcd17/p2a0 through lcd19/p2a2 pins are set in the general purpose input port. the com0 through com3 pins also output a low level. therefore, the lcd display is off. the lcd segment register retains the previous contents. 19.8.4 in halt status the lcd0 through lcd19 pins output segment signals. the com0 through com3 pins output common signals. the lcd segment register retains the previous contents.
208 m pd17933, 17934 20. standby the standby function is used to reduce the current consumption of the device while the device is backed up. 20.1 outline of standby function figure 20-1 outlines the standby block. the standby function reduces the current consumption of the device by partly or totally stopping the device operation. the following two types of standby functions are available for selection as the application requires. ? halt function ? clock stop function the halt function reduces the current consumption of the device by stopping the cpu operation by using a dedicated instruction halt h. the clock stop function reduces the current consumption of the device by stopping the oscillation of the oscillation circuit by using a dedicated instruction stop s. figure 20-1. outline of standby block interrupt control block btm0cy p0d3/ad2 p0d2/ad1 p0d1/ad0 p0d0 input latch oscillation circuit x out x in halt control circuit halt h clock stop control circuit stop s cpu program counter alu system register control register instruction decoder
209 m pd17933, 17934 operand halt h (4 bits) b 3 b 2 b 1 b 0 0 1 released when high level is input to port 0d released when basic timer 0 carry ff is set to 1 undefined (fix this bit to ??) released when interrupt is accepted not released even if condition is satisfied released if condition is satisfied sets halt status releasing condition 20.2 halt function 20.2.1 outline of halt function the halt function stops the operating clock of the cpu by executing the halt h instruction. when this instruction is executed, the program is stopped until the halt status is later released. therefore, the current consumption of the device in the halt status is reduced by the operating current of the cpu. the halt status is released by using basic timer 0 carry ff, interrupt, or port input (p0d). the release condition is specified by operand h of the halt h instruction. 20.2.2 halt status in the halt status, all the operations of the cpu are stopped. in other words, execution of the program is stopped at the halt h instruction. however, the peripheral hardware units continue the operation specified before execution of the halt h instruction. for the operation of each peripheral hardware unit, refer to 20.4 device operation in halt and clock stop status . 20.2.3 halt release condition figure 20-2 shows the halt release condition. the halt release condition is specified by 4-bit data specified by operand h of the halt h instruction. the halt status is released when the condition specified by 1 in operand h. when the halt status is released, program execution is started from the instruction after the halt h instruction. if the halt status is released by an interrupt, the operation to be performed after the halt status has been released differs depending on whether the interrupts are enabled (ei status) or disabled (di status) when an interrupt source (irqxxx = 1) is issued with the interrupt (ipxxx = 1) enabled. if two or more releasing conditions are specified, the halt status is released when one of the specified condition is satisfied. if 0000b is set as halt release condition h, no releasing condition is set. if the device is reset at this time, the halt status is released. figure 20-2. halt release condition
210 m pd17933, 17934 20.2.4 releasing halt by input port (p0d) the halt releasing condition using an input port is specified by the halt 0001b instruction. when the halt releasing condition using an input port is specified, the halt status is released if a high level is input to one of the p0d0 through p0d3 pins. the p0d0 through p0d3 pins are multiplexed with the a/d converter input pins ad0 through ad2 (except p0d0) and the halt status is not released when these pins are used as a/d converter input pins. an example is given below. ? to use as key matrix the p0d0 through p0d3 pins are general-purpose input port pins which can be set in the input or output mode in 1-bit units and can be connected to an internal pull-down resistor. if connection of the internal pull-down resistor is specified by software, an external resistor can be eliminated as shown in this example (the internal- pull down resistor is connected at reset by the reset pin.) the halt 0001b instruction is executed after the general-purpose output ports for key source signal are made high. note that if an alternate switch is used as shown by switch a in the above figure, the halt status is released immediately because a high level is input to the p0d0 pin while switch a is closed. p0d3/ad2 p0dpld3 flag p0d2/ad1 p0d1/ad0 p0d0 switch a general-purpose output port latch
211 m pd17933, 17934 20.2.5 releasing halt status by basic timer 0 carry ff releasing the halt status by using the basic timer 0 carry ff is specified by the halt 0010b instruction. when releasing the halt status by the basic timer 0 carry ff is specified, the halt status is released as soon as the basic timer 0 carry ff has been set to 1. the basic timer 0 carry ff corresponds to the btm0cy flag on a one-to-one basis and is set at fixed time intervals (125 ms). therefore, the halt status can be released at fixed time intervals. example to release halt status every 125 ms to execute processing a hlttmr dat 0010b ; symbol definition loop: halt hlttmr ; specifies setting of basic timer 0 carry ff as halt releasing condition skt1 btmocy ; embedded macro br loop ; branches to loop if btm0cy flag is not set processing a ; executes processing a if carry occurs br loop 20.2.6 releasing halt status by interrupt releasing the halt status by an interrupt is specified by the halt 1000b instruction. when releasing the halt status by an interrupt is specified, the halt status is released as soon as the interrupt has been accepted. many interrupt sources are available as described in 12. interrupts. which interrupt source is used to release the halt status must be specified in advance in software. to accept an interrupt, each interrupt request must be issued from each interrupt source and each interrupt must be enabled (by setting the corresponding interrupt enable flag). therefore, the interrupt is not accepted even if the interrupt request is issued, and the halt status is not released. when the halt status is released by accepting an interrupt, the program flow branches to the vector address of the interrupt. when the reti instruction is executed after interrupt servicing, the program flow is restored to the instruction after the halt instruction. if all the interrupts are disabled (di status), the halt status is released by enabling an interrupt (ipxxx = 1) and issuing an interrupt source (irqxxx = 1), and the flow of the program goes to the instruction after the halt instruction.
212 m pd17933, 17934 example releasing halt status by timer 0 and int pin interrupts in this example, the halt status is released and processing b is executed when timer 0 interrupt is accepted. and processing a is executed when int pin interrupt is accepted. each time the halt status has been released, processing c is executed. hltint dat 1000b ; symbol definition start: ; address 0000h br main ;*** interrupt vector address *** nop ; sio2 nop ; basic timer 1 br inttm0 ; branches to timer 0 interrupt processing intp: ; branches to int pin interrupt processing ; int pin interrupt vector address (0004h) processing a ; int pin interrupt processing ei reti inttm0: processing b ; timer 0 interrupt processing ei reti main: initflg tmock1, tm0ck0 ; sets timer 0 count clock to 40 m s mov dbf1, #0 mov dbf0, #32h put tm0m,dbf ; sets time interval of timer 0 interrupt to 2 ms set2 tm0res, tm0en ; resets and starts timer 0 set2 iptm0, ip0 ; enables int pin and timer 0 interrupts loop: processing c ; main routine processing ei ; enables all interrupts halt hltint ; specifies releasing halt status by interrupt ;<1> br loop if the int pin interrupt request and timer 0 interrupt request are issued simultaneously in the halt status, processing a for the int pin, which has the higher hardware priority, is executed. after execution of processing a and when reti is executed, the program branches to the br loop instruction of <1>. however, the br loop instruction is not executed, and timer 0 interrupt is immediately accepted. when the reti instruction is executed after processing b of timer 0 interrupt has been executed, the br loop instruction is executed.
213 m pd17933, 17934 caution to reset the interrupt request flag (irqxxx) once before the halt instruction is executed, insert a nop instruction (or one or more other instructions) between the halt instruction and the instruction that resets the interrupt request flag (irqxxx) as shown below. if a nop instruction (or one or more other instructions) is not inserted, the interrupt request flag is not reset, and therefore, the halt status is released immediately. example : : ; irqxxx is set at certain timing : clr1 irq ; resets irqxxx flag once nop ; resets irqxxx flag at this timing ; unless this period is missing, the irqxxx flag is not reset, ; and the next halt instruction is immediately released halt 1000b ;
214 m pd17933, 17934 20.2.7 if two or more releasing conditions are specified at same time if two or more halt releasing conditions are specified at same time, the halt status is released when one of the conditions is satisfied. the following program example shows how the releasing conditions are identified if two or more conditions are satisfied at the same time. example hltintp dat 1000b hltbtm dat 0010b hltp0d dat 0001b p0d mem 0.73h start: br main ;*** interrupt vector address *** nop ; si0 nop ; basic timer 1 nop ; tm0 nop ; int intp: ; int pin interrupt vector address (0004h) processing a ; int pin interrupt processing ei reti btmoup: ; timer carry ff processing processing b ret p0dp: ; p0d input processing processing c ret main: set1 ip0 ; enables int pin interrupt ei loop: halt hltint or hltbtm or hltp0c ; selects interrupt, timer carry ff (125 ms), and p0d input as halt releasing conditions skf1 btm0cy ; detects btm0cy flag call btm0up ; timer carry ff processing if flag is set to 1 skf p0d, 1111b ; detects p0d input call p0dp ; port input processing if p0d is high br loop
215 m pd17933, 17934 in the above example, three halt status releasing conditions, int pin interrupt, 125-ms basic timer 0 carry ff, and port 0d input, are specified. to identify which condition has released the halt status, a vector address (interrupt), btm0cy flag (timer carry ff), and port register (port input) are detected. to use two or more releasing conditions, the following two points must be noted. ? when the halt status is released, all the specified releasing conditions must be detected. ? the releasing condition with the higher priority must be detected first. 20.3 clock stop function 20.3.1 outline of clock stop function the clock stop function stops the oscillation circuit of a 75-khz crystal resonator by executing the stop s instruction (clock stop status). therefore, the current consumption of the device is reduced to 10 m a max (t a = C10 to +50 c, v dd = 1.05 to.1.8 v) 20.3.2 clock stop status in the clock stop status, all the device operations of the cpu and peripheral hardware units are stopped because the generation circuit of the crystal resonator is stopped. for the operations of the cpu and peripheral hardware units, refer to 20.4 device operation in halt and clock stop status . 20.3.3 releasing clock stop status figure 20-3 shows the stop status releasing conditions. the stop status releasing condition is specified by 4-bit data specified by operand s of the stop s instruction. the stop status is released when the condition specified by 1 in operand s is satisfied. when the stop status has been released, a halt period which is half the time (t set /2) specified by the basic timer 0 clock selection register as oscillation circuit stabilization wait time has elapsed, and the program execution is started from the instruction next to the stop s instruction. if releasing the stop status by an interrupt is specified, however, the program operation after the stop status has been released differs depending on whether the interrupt is enabled (ei status) or disabled (di status) when an interrupt source is issued (irqxxx = 1) with the interrupt enabled (ipxxx = 1). if all the interrupts are enabled (ei status), the stop status is released when the interrupt is enabled (ipxxx = 1) and the interrupt source is issued (irqxxx = 1), and the program flow returns to the instruction next to the stop instruction. if all the interrupts are disabled (di status), the stop status is released when the interrupt is enabled (ipxxx = 1) and the interrupt resource is issued (irqxxx = 1), and the program flow returns to the instruction next to the stop instruction. if two or more releasing conditions are specified at one time, and if one of the conditions is satisfied, the stop status is released. if 0000b is specified as stop releasing condition s, no releasing condition is satisfied. if the device is reset at this time the stop status is released.
216 m pd17933, 17934 figure 20-3. stop releasing conditions 20.3.4 releasing clock stop status by high level input of port 0d figure 20-4 illustrates how the clock stop status is released by the high level input to port 0d. figure 20-4. releasing clock stop status by high level input of port 0d v dd p0d x out 5 v 0 v h l 2.2 v stop s instruction starts from instruction next to stop s oscillation stops t set /2 halt period t set : basic timer 0 setting time operand stop s (4 bits) b 3 b 2 b 1 b 0 0 1 releases when high level is input to port 0d undefined (fix this bit to ??) undefined (fix this bit to ??) released by interrupt of int pin not released even if condition is statisfied released if condition is satisfied specifies stop status releasing condition
217 m pd17933, 17934 20.4 device operation in halt and clock stop status table 20-1 shows the operations of the cpu and peripheral hardware units in the halt and clock stop status. in the halt status, all the peripheral hardware units continue the normal operation until instruction execution is stopped. in the clock stop status, all the peripheral hardware units stop operation. the control registers that control the operations of the peripheral hardware units operate normally (not initialized) in the halt status, but are initialized to specified values when the clock stop instruction is executed. in other words, all peripheral hardware continues the operation specified by the control register in the halt status, and the operation is determined by the initialized value of the control register in the clock stop status. for the values of the control registers in the clock stop status, refer to 8. register file (rf) and control register . table 20-1. device operation in halt and clock stop status peripheral hardware status halt clock stop program counter stops at address of halt instruction stops at address of stop instruction system register retained retained peripheral register retained partly initialized note control register retained partly initialized note timer normal operation operation stops pll frequency synthesizer normal operation operation stops a/d converter normal operation operation stops serial interface stops operation when internal clock (master) stops operation and used as general- is selected and continues operation when purpose i/o port external clock (slave) is selected frequency counter normal operation stops operation and used as general- purpose input port beep output normal operation stops operation and used as general- purpose i/o port lcd controller/driver normal operation stops operation general-purpose i/o port normal operation retained general-purpose input port normal operation input port general-purpose output port normal operation retains output latch note for the value to which these registers are initialized, refer to 5. system register (sysreg) and 8. register file (rf) and control register . 20.5 cautions on processing of each pin in halt and clock stop status the halt status is used to reduce the current consumption when, say, only the watch is used. the clock stop function is used to reduce the current consumption of the device to only use the data memory. therefore, the current consumption must be reduced as much as possible in the halt status or clock stop status. at this time, the current consumption significantly varies depending on the status of each pin, and the points shown in table 20-2 must be noted.
218 m pd17933, 17934 table 20-2. status of each pin in halt and clock stop status and cautions (1/2) pin function pin symbol status of each pin and cautions on processing halt status clock stop status general- port 0b p0b3/beep purpose p0b2/so1 i/o port p0b1/si1/so2 p0b0/sck port 1a p1a3 p1a2 p1a1 p1a0 port 1d p1d3 p1d2 p1d1 p1d0 port 2b p2b3-p2b0 port 2c p2c3-p2c0 general- port 0d p0d3/ad2 purpose p0d2/ad1 input port p0d1/ad0 p0d0 port 1c p1c3/fmifc/amifc p1c2/amifc p1c1/tm1 p1c0/tm0 port 2a p2a2/lcd19 p2a1/lcd18 p2a0/lcd17 general- port 0a p0a1 purpose p0a0 output port port 0c p0c3-p0c0 retains status before halt (1) when specified as output pin current consumption increases if pin is externally pulled down while it outputs high level, or externally pulled up while it outputs low level. exercise care in using n-ch open- drain output (p1a3-p1a0, p1d3- p1d0) (2) when specified as input pin current consumption increases due to noise if pin is floated (3) port 0d (p0d3/ad1-p0d1/ad0, p0d0) current consumption increases if pin is externally pulled up because it is provided with pull-down resistor selectable by software (4) port 1c (p1c3/fmifc/amifc, p1c2/amifc, p1c1/tm1, p1c0/tm0) when p1c2/amifc or p1c3/fmifc/ amifc pin is used for if counter, current consumption increases because internal amplifier operates all port pins are set in general-purpose port mode (except p0d3/ad2- p0d1/ad0, p2a2/lcd19-p2a0/lcd17) input or output mode of general-purpose i/o port set before clock stop status is retained. (1) when specified as general-purpose output port current consumption increases due to noise if pin is floated (2) when specified as general-purpose input port current consumption does not increase due to noise even if pin is floated (3) p0d3/ad2-p0d1/ad0 pin used for a/d converter is retained as is. pull-down resistor of p0d3- p0d0 pin retains previous status (4) p2a2/lcd19-p2a0/lcd17 pin used for lcd segment is retained as is. specified as general-purpose output port. output contents are retained as is. if pin is externally pulled down while it outputs high level or externally pulled up while it outputs low level, current consumption increases
219 m pd17933, 17934 table 20-2. status of each pin in halt and clock stop status and cautions (2/2) pin function pin symbol status of each pin and cautions on processing halt status clock stop status external interrupt int current consumption increases due to noise if pin is floated pll frequency vcol synthesizer vcoh eo0 eo1 crystal oscillation x in circuit x out lcd controller/driver lcd19/p2a2 lcd18/p2a1 lcd17/p2a0 lcd16 | lcd0 com3 | com0 current consumption increases during pll operation. when pll is disabled, pin is in following status: vcoh, vcol : internally pulled down eo1, eo0 : floated pll is disabled vcoh, vcol : internally pulled down eo1, eo0 : floated current consumption changes due to oscillation waveform of crystal oscillation circuit. the higher oscillation amplitude, the lower current consumption. oscillation amplitude must be evaluated because it is influenced by crystal resonator or load capacitor used (1) when lcd19/p2a2-lcd17/p2a0 are used as general-purpose input port pins when these pins are used as general- purpose input port pins, the same points as described above must be noted. (2) when lcd controller/driver is used (lcden = 1) lcd19-lcd0 : output segment signals com3-com0 : output common signals (3) lcd display off (lcden = 0) lcd19-lcd0 : output segment signals com3-com0 : output common signals x in pin is internally pulled down, and x out pin outputs high level (1) when lcd19/p2a2-lcd17/p2a0 are used as general-purpose input port pins when these pins are used as general- purpose input port pins, the same points as described above must be noted. (2) when lcd controller/driver is used lcden = 0 lcd16-lcd0 : output low level com3-com0 : output low level
220 m pd17933, 17934 21. reset 21.1 outline of reset the reset function is used to initialize the device. the m pd17934 can be reset in the following ways: ? reset by reset pin ? wdt&sp reset figure 21-1. configuration of reset block x out x in reset falling detection circuit timer ff block divider basic timer 0 carry reset control circuit watchdog timer, stack overflow/underflow detection block wdt&sp reset signal stop instruction
221 m pd17933, 17934 21.2 reset by reset pin when a low level is input to the reset pin, an internal reset signal is generated. at this point, the program counter, stack, system registers, and control registers are initialized (for the initial value, refer to the description of each register). when the reset pin is raised next time, the program starts from address 0 at the rising edge of the basic timer 0 carry ff setting signal 125 ms after a high level has been input to the reset pin. if reset is executed by the reset pin during program execution, the data in the data memory may be lost. figure 21-2. reset operation by reset pin v dd reset x out btm0cy flag setting pulse 1.8 v 0 v h l h l h l device opeation stops halt status 125 ms program starts from address 0 low-level is input to reset pin high-level is input to reset pin
222 m pd17933, 17934 21.3 wdt&sp reset wdt&sp reset includes the following: ? watchdog timer reset ? stack pointer overflow/underflow reset figure 21-3. outline of wdt&sp reset 21.3.1 watchdog timer reset the watchdog timer is a circuit that generates a reset signal when the execution sequence of the program is abnormal (hung-up). hanging-up means that the program jumps to an unexpected routine due to external noise, entering a specific infinite loop and causing the system to be deadlocked. by using the watchdog timer, the program can be restored from this hang-up status because a reset signal is generated from the watchdog timer at fixed time intervals and program execution is started from address 0. the watchdog timer does not function in the clock stop mode and halt mode. resetting by the watchdog timer initializes all the registers except the stack overflow selection register, watchdog timer counter reset register, and basic timer 0 carry register. the watchdog timer reset is detected by the wdtspres flag (r&reset). instruction count clock 4096 instruction counter 8192 instruction counter stack overflow/under flow reset detection circuit wdtres sprsel0 flag sprsel1 flag wdtck1 flag wdtck0 falg wdtspres flag wdt&sp reset signal
223 m pd17933, 17934 21.3.2 watchdog timer setting flags these flags can be set only once after power-on reset on power application or reset by the reset pin. the wdtck0 and wdtck1 flags select an interval at which the reset signal is output. the reference time can be selected to the following three conditions: ? 4096 instructions ? 8192 instructions ? watchdog timer not set on power application, 8192 instructions are selected. if the reset signal generation interval is specified to be 8192 instructions, the watchdog timer ff must be reset at intervals not exceeding 8192 instructions. the valid reset period is from 1 to 8192 instructions. if the reset signal generation interval is 4096 instructions, the watchdog timer ff must be reset at intervals not exceeding 4096 instrutions. the valid reset period is from 1 to 4096 instructions. figure 21-4. configuration of watchdog timer clock selection register note can be written only once. name flag symbol b 3 0 b 2 0 b 1 w d t c k 1 b 0 w d t c k 0 address (bank15) 02h read/write r/w note watchdog timer clock selection reset by reset pin wdt&sp reset clock stop at reset 0011 0 1 0 1 does not set watchdog timer 4096 instructions setting prohibited 8192 instructions selects clock of watchdog timer fixed to ? 0 0 1 1 retained retained
224 m pd17933, 17934 the wdtres flag is used to reset the watchdog timer counter. when this flag is set to 1, the watchdog timer counter is automatically reset. if the wdtres flag is set to 1 once within a reference time in which the wdtck0 and wdtck1 flags are set, the reset signal is not output by the watchdog timer. figure 21-5. configuration of watchdog timer counter reset register name flag symbol b 3 w d t r e s b 2 0 b 1 0 b 0 0 address (bank15) 03h read/write w&reset watchdog timer counter reset reset by reset pin wdt&sp reset clock stop at reset u u u 000 0 1 invalid resets watchdog timer counter resets watchdog timer counter fixed to ? u: undefined
225 m pd17933, 17934 21.3.3 stack pointer overflow/underflow reset a reset signal is generated if the address or interrupt stack overflows or underflows. stack pointer overflow/underflow reset can be used to detect a program hang-up in the same manner as watchdog timer reset. the reset signal is generated under the following conditions: ? interrupt due to overflow or underflow of interrupt stack (4 levels) ? interrupt due to overflow or underflow of address stack (15 levels) reset by stack pointer overflow or underflow initializes all the registers, except the stack overflow selection register, watchdog timer counter reset register, and basic timer 0 carry register. generation of stack pointer overflow or underflow reset is detected by the wdtspres flag (r&reset). 21.3.4 stack pointer setting flag the stack overflow/underflow reset selection register can be set only once after reset by the reset pin. this register specifies whether reset by address stack overflow or underflow and reset by interrupt stack overflow or underflow are enabled or disabled.
226 m pd17933, 17934 figure 21-6. configuration of stack overflow/underflow reset selection register note can be written only once. name flag symbol b 3 0 b 2 0 b 1 s p r s e l 1 b 0 s p r s e l 0 address (rf) 05h read/write r/w note stack overflow/underflow reset selection reset by reset pin wdt&sp reset clock stop at reset 0011 0 1 disables reset enables reset selects address stack overflow/underflow reset 0 1 disables reset enables reset selects interrupt stack overflow/underflow reset fixed to ? retained retained
227 m pd17933, 17934 figure 21-7. configuration of wdt&sp reset selection register name flag symbol b 3 0 b 2 0 b 1 0 b 0 w d t s p r e s address (bank15) 16h read/write r&reset wdt&sp reset status detection reset by reset pin wdt&sp reset clock stop at reset 0000 1 r 0 1 no reset request reset request detects occurrence of wdt&sp reset fixed to ? r: retained
228 m pd17933, 17934 22. instruction set 22.1 outline of instruction set b 14 -b 11 b 15 01 bin hex 0000 0 add r,m add m,#n4 0001 1 sub r,m sub m, #n4 0010 2 addc r,m addc m,#n4 0011 3 subc r,m subc m,#n4 0100 4 and r,m and m,#n4 0101 5 xor r,m xor m,#n4 0110 6 or r,m or m,#n4 inc ar inc ix rorc r movt dbf,@ar push ar pop ar get dbf,p put p,dbf peek wr,rf poke rf,wr 0111 7 br @ar call @ar ret retsk reti ei di stop s halt h nop 1000 8 ld r,m st m,r 1001 9 ske m,#n4 skge m,#n4 1010 a mov @r,m mov m,@r 1011 b skne m,#n4 sklt m,#n4 1100 c br addr (page 0) call addr (page 0) 1101 d br addr (page 1) mov m,#n4 1110 e br addr (page 2) skt m,#n4 1111 f br addr (page 3) skf m,#n
229 m pd17933, 17934 22.2 legend ar : address register asr : address stack register indicated by stack pointer addr : program memory address (low-order 11 bits) bank : bank register cmp : compare flag cy : carry flag dbf : data buffer h : halt release condition intef : interrupt enable flag intr : register automatically saved to stack when interrupt occurs intsk : interrupt stack register ix : index register mp : data memory row address pointer mpe : memory pointer enable flag m : data memory address indicated by m r , m c m r : data memory row address (high-order) m c : data memory column address (low-order) n : bit position (4 bits) n4 : immediate data (4 bits) page : page (bits 12 and 11 of program counter) pc : program counter p : peripheral address p h : peripheral address (high-order 3 bits) p l : peripheral address (low-order 4 bits) r : general register column address rf : register file address rf r : register file row address (high-order 3 bits) rf c : register file column address (low-order 4 bits) sp : stack pointer s : stop release condition wr : window register (x) : contents addressed by x
230 m pd17933, 17934 22.3 instruction list instructions mnemonic operand operation instruction code op code operand add add r,m (r) ? (r) + (m) 00000 m r m c r m,#n4 (m) ? (m) + n4 10000 m r m c n4 addc r,m (r) ? (r) + (m) + cy 00010 m r m c r m,#n4 (m) ? (m) + n4 + cy 10010 m r m c n4 inc ar ar ? ar + 1 00111 000 1001 0000 ix ix ? ix + 1 00111 000 1000 0000 subtract sub r,m (r) ? (r) C (m) 00001 m r m c r m,#n4 (m) ? (m) C n4 10001 m r m c n4 subc r,m (r) ? (r) C (m) C cy 00011 m r m c r m,#n4 (m) ? (m) C n4 C cy 10011 m r m c n4 logical or r,m (r) ? (r) v (m) 00110 m r m c r operation m,#n4 (m) ? (m) v n4 10110 m r m c n4 and r,m (r) ? (r) (m) 00100 m r m c r m,#n4 (m) ? (m) n4 10100 m r m c n4 xor r,m (r) ? (r) v (m) 00101 m r m c r m,#n4 (m) ? (m) v n4 10101 m r m c n4 judge skt m,#n cmp ? 0, if (m) n = n, then skip 11110 m r m c n skf m,#n cmp ? 0, if (m) n = 0, then skip 11111 m r m c n compare ske m,#n4 (m) C n4, skip if zero 01001 m r m c n4 skne m,#n4 (m) C n4, skip if not zero 01011 m r m c n4 skge m,#n4 (m) C n4, skip if not borrow 11001 m r m c n4 sklt m,#n4 (m) C n4, skip if borrow 11011 m r m c n4 rotate rorc r cy ? (r) b 3 ? (r) b 2 ? (r) b 1 ? (r) b 0 00111 000 0111 r transfer ld r,m (r) ? (m) 01000 m r m c r st m,r (m) ? (r) 11000 m r m c r mov @r,m if mpe = 1 : (mp, (r)) ? (m) 01010 m r m c r if mpe = 0 : (bank, m r , (r)) ? (m) m, @r if mpe = 1 : (m) ? (mp, (r)) 11010 m r m c r if mpe = 0 : (m) ? (bank, m r , (r)) m,#n4 (m) ? n4 11101 m r m c n4 movt dbf,@ar sp ? sp C 1, asr ? pc, pc ? ar, 00111 000 0001 0000 dbf ? (pc), pc ? asr, sp ? sp + 1 push ar sp ? sp C 1, asr ? ar 00111 000 1101 0000 pop ar ar ? asr, sp ? sp + 1 00111 000 1100 0000 get dbf,p dbf ? (p) 00111 p h 1011 p l put p,dbf (p) ? dbf 00111 p h 1010 p l peek wr,rf wr ? (rf) 00111 rf r 0011 rf c poke rf,wr (rf) ? wr 00111 rf r 0010 rf c v v v v
231 m pd17933, 17934 instructions mnemonic operand operation instruction code op code operand branch br addr pc 10C0 ? addr, page ? 0 01100 addr pc 10C0 ? addr, page ? 1 01101 pc 10C0 ? addr, page ? 201110 pc 10C0 ? addr, page ? 3 01111 @ar pc ? ar 00111 000 0100 0000 subroutine call addr sp ? sp C 1, asr ? pc 11100 addr pc 11 ? 0, pc 10C0 ? addr @ar sp ? sp C 1, asr ? pc 00111 000 0101 0000 pc ? ar ret pc ? asr, sp ? sp + 1 00111 000 1110 0000 retsk pc ? asr, sp ? sp + 1 and skip 00111 001 1110 0000 reti pc ? asr, intr ? intsk, sp ? sp + 1 00111 010 1110 0000 interrupt ei intef ? 1 00111 000 1111 0000 di intef ? 0 00111 001 1111 0000 others stop s stop 00111 010 1111 s halt h halt 00111 011 1111 h nop no operation 00111 100 1111 0000
232 m pd17933, 17934 22.4 assembler (ra17k) embedded macro instruction legend flag n : flg symbol n : bit number < > : can be omitted mnemonic operand operation n embedded sktn flag 1, ... flag n if (flag1) ~ (flag n) = all 1, then skip 1 n 4 macro skfn flag 1, ... flag n if (flag 1) ~ (flag n) = all 0, then skip 1 n 4 setn flag 1, ... flag n (flag 1) ~ (flag n) ? 11 n 4 clrn flag 1, ... flag n (flag 1) ~ (flag n) ? 01 n 4 notn flag 1, ... flag n if (flag n) = 0, then (flag n) ? 11 n 4 if (flag n) = 1, then (flag n) ? 0 initflg flag 1, if description = not flag n, then (flag n) ? 01 n 4 ... < flag n> if description = flag n, then (flag n) ? 1 bankn (bank) ? n0 n 15 expanded brx label jump label instruction callx function-name call sub-routine syscalx function-name or call system sub-routine expression initflgx flag 1, if description = not (or inv) n 4 ... flag n flag, (flag) ? 0 if description = flag, (flag) ? 1
233 m pd17933, 17934 23. reserved symbols 23.1 data buffer (dbf) symbol name attribute value r/w description dbf3 mem 0.0ch r/w bits 15 through 12 of data buffer dbf2 mem 0.0dh r/w bits 11 through 8 of data buffer dbf1 mem 0.0eh r/w bits 7 through 4 of data buffer dbf0 mem 0.0fh r/w bits 3 through 0 of data buffer 23.2 system registers (sysreg) symbol name attribute value r/w description ar3 mem 0.74h r/w bits 15 through 12 of address register ar2 mem 0.75h r/w bits 11 through 8 of address register ar1 mem 0.76h r/w bits 7 through 4 of address register ar0 mem 0.77h r/w bits 3 through 0 of address register wr mem 0.78h r/w window register bank mem 0.79h r/w bank register ixh mem 0.7ah r/w bits 10 through 8 of index register mph mem 0.7ah r/w bits 6 through 4 of memory pointer mpe flg 0.7ah.3 r/w memory pointer enable flag ixm mem 0.7bh r/w bits 7 through 4 of index register mpl mem 0.7bh r/w bits 3 through 0 of memory pointer ixl mem 0.7ch r/w bits 3 through 0 of index register rph mem 0.7dh r/w bits 6 through 3 of general register pointer rpl mem 0.7eh r/w bits 2 through 0 of general register pointer bcd flg 0.7eh.0 r/w bcd operation flag psw mem 0.7fh r/w program status word cmp flg 0.7fh.3 r/w compare flag cy flg 0.7fh.2 r/w carry flag z flg 0.7fh.1 r/w zero flag ixe flg 0.7fh.0 r/w index enable flag
234 m pd17933, 17934 23.3 lcd segment register symbol name attribute value r/w description lcdd19 mem 14.5ch r/w lcd segment register lcdd18 mem 14.5dh r/w lcd segment register lcdd17 mem 14.5eh r/w lcd segment register lcdd16 mem 14.5fh r/w lcd segment register lcdd15 mem 14.60h r/w lcd segment register lcdd14 mem 14.61h r/w lcd segment register lcdd13 mem 14.62h r/w lcd segment register lcdd12 mem 14.63h r/w lcd segment register lcdd11 mem 14.64h r/w lcd segment register lcdd10 mem 14.65h r/w lcd segment register lcdd9 mem 14.66h r/w lcd segment register lcdd8 mem 14.67h r/w lcd segment register lcdd7 mem 14.68h r/w lcd segment register lcdd6 mem 14.69h r/w lcd segment register lcdd5 mem 14.6ah r/w lcd segment register lcdd4 mem 14.6bh r/w lcd segment register lcdd3 mem 14.6ch r/w lcd segment register lcdd2 mem 14.6dh r/w lcd segment register lcdd1 mem 14.6eh r/w lcd segment register lcdd0 mem 14.6fh r/w lcd segment register
235 m pd17933, 17934 23.4 port register symbol name attribute value r/w description p0a1 flg 0.70h.1 r/w port 0a bit 1 p0a0 flg 0.70h.0 r/w port 0a bit 0 p0b3 flg 0.71h.3 r/w port 0b bit 3 p0b2 flg 0.71h.2 r/w port 0b bit 2 p0b1 flg 0.71h.1 r/w port 0b bit 1 p0b0 flg 0.71h.0 r/w port 0b bit 0 p0c3 flg 0.72h.3 r/w port 0c bit 3 p0c2 flg 0.72h.2 r/w port 0c bit 2 p0c1 flg 0.72h.1 r/w port 0c bit 1 p0c0 flg 0.72h.0 r/w port 0c bit 0 p0d3 flg 0.73h.3 r note port 0d bit 3 p0d2 flg 0.73h.2 r note port 0d bit 2 p0d1 flg 0.73h.1 r note port 0d bit 1 p0d0 flg 0.73h.0 r note port 0d bit 0 p1a3 flg 1.70h.3 r/w port 1a bit 3 p1a2 flg 1.70h.2 r/w port 1a bit 2 p1a1 flg 1.70h.1 r/w port 1a bit 1 p1a0 flg 1.70h.0 r/w port 1a bit 0 p1c3 flg 1.72h.3 r note port 1c bit 3 p1c2 flg 1.72h.2 r note port 1c bit 2 p1c1 flg 1.72h.1 r note port 1c bit 1 p1c0 flg 1.72h.0 r note port 1c bit 0 p1d3 flg 1.73h.3 r/w port 1d bit 3 p1d2 flg 1.73h.2 r/w port 1d bit 2 p1d1 flg 1.73h.1 r/w port 1d bit 1 p1d0 flg 1.73h.0 r/w port 1d bit 0 p2a2 flg 2.70h.2 r/w port 2a bit 2 p2a1 flg 2.70h.1 r/w port 2a bit 1 p2a0 flg 2.70h.0 r/w port 2a bit 0 p2b3 flg 2.71h.3 r/w port 2b bit 3 p2b2 flg 2.71h.2 r/w port 2b bit 2 p2b1 flg 2.71h.1 r/w port 2b bit 1 p2b0 flg 2.71h.0 r/w port 2b bit 0 p2c3 flg 2.72h.3 r/w port 2c bit 3 p2c2 flg 2.72h.2 r/w port 2c bit 2 p2c1 flg 2.72h.1 r/w port 2c bit 1 p2c0 flg 2.72h.0 r/w port 2c bit 0 note these ports are input-only ports. the assembler and in-circuit emulator will not output error messages even if an instruction to output from these ports is written. also, if the instruction is actually executed on a device, the operation will have no change.
236 m pd17933, 17934 23.5 register file (control register) symbol name attribute value r/w description sp mem 0.81h r/w stack pointer dbfsp mem 0.84h r dbf stack pointer sprsel mem 0.85h r/w stack overflow select flag (settable only once after power application) movtsel1 flg 0.87h.1 r/w movt bit select flag movtsel0 flg 0.87h.0 r/w movt bit select flag sysrsp mem 0.88h r system register stack pointer wdtck mem 15.02h r/w watchdog timer clock select flag wdtres flg 15.03h.3 r/w watchdog timer count reset pllscnf flg 15.10h.3 r/w swallow counter msb set flag pllmd1 flg 15.10h.1 r/w pll mode select flag pllmd0 flg 15.10h.0 r/w pll mode select flag pllrfck3 flg 15.11h.3 r/w pll reference frequency select flag pllrfck2 flg 15.11h.2 r/w pll reference frequency select flag pllrfck1 flg 15.11h.1 r/w pll reference frequency select flag pllrfck0 flg 15.11h.0 r/w pll reference frequency select flag pllul flg 15.12h.0 r pll unlock ff flag beep0sel flg 15.14h.2 r/w beep0 enable flag beep0ck1 flg 15.14h.1 r/w beep0 clock select flag beep0ck0 flg 15.14h.0 r/w beep0 clock select flag wdtcy flg 15.16h.0 r watchdog timer/stack pointer reset status detection flag btm0cy flg 15.17h.0 r basic timer 0 carry flag btm1ck0 flg 15.18h.0 r/w basic timer 1 clock select flag sio1ck1 flg 15.1ch.1 r/w serial interface 1 i/o clock select flag sio1ck0 flg 15.1ch.0 r/w serial interface 1 i/o clock select flag sio1mod flg 15.1dh.2 r/w serial interface 1 si1/so2 select flag sio1hiz flg 15.1dh.1 r/w serial interface 1 general-purpose port select flag sio1ts flg 15.1dh.0 r/w serial interface 1 transmit/receive start flag ieg0 flg 15.1fh.0 r/w int0 pin interrupt request detection edge direction select flag ifcg0stt flg 15.21h.0 r if counter gate status detection flag (1: open, 0: close) ifcmd1 flg 15.22h.3 r/w if counter mode select flag (10: fmifc, 11: amifc2) ifcmd0 flg 15.22h.2 r/w if counter mode select flag (00: fcg, 01: amifc) ifcck1 flg 15.22h.1 r/w if counter clock select flag ifcck0 flg 15.22h.0 r/w if counter clock select flag ifcstrt flg 15.23h.1 w if counter count start ifcres flg 15.23h.0 r/w if counter reset
237 m pd17933, 17934 symbol name attribute value r/w description adcch3 flg 15.24h.3 r/w a/d converter channel select flag adcch2 flg 15.24h.2 r/w a/d converter channel select flag adcch1 flg 15.24h.1 r/w a/d converter channel select flag adcch0 flg 15.24h.0 r/w a/d converter channel select flag adcstrt flg 15.25h.1 r/w a/d converter compare start flag adccmp flg 15.25h.0 r a/d converter compare result detection flag tm0en flg 15.2bh.3 r/w modulo timer 0 count start flag tm0res flg 15.2bh.2 r/w modulo timer 0 reset flag (the value is 0 when read) tm0ck1 flg 15.2bh.1 r/w modulo timer 0 clock select flag (10: tm10, 11: tm11) tm0ck0 flg 15.2bh.0 r/w modulo timer 0 clock select flag (00: 75 khz, 01: 25 khz) tm0ovf flg 15.2ch.3 r modulo timer 0 overflow detection flag ipsio1 flg 15.2fh.3 r/w serial interface 1 interrupt enable flag ipbtm1 flg 15.2fh.2 r/w basic timer 1 interrupt enable flag iptm0 flg 15.2fh.1 r/w modulo timer 0 interrupt enable flag ip0 flg 15.2fh.0 r/w int0 pin interrupt enable flag irqsio1 flg 15.3ch.0 r/w serial interface 1 interrupt request detection flag irqbtm1 flg 15.3dh.0 r/w basic timer 1 interrupt request detection flag irqtm0 flg 15.3eh.0 r/w modulo timer 0 interrupt request detection flag int0 flg 15.3fh.3 r/w int0 pin status detection flag irq0 flg 15.3fh.0 r/w int0 pin interrupt request detection flag lcden flg 15.40h.0 r/w lcd driver display start flag lcd19sel flg 15.69h.2 r/w p2a2/lcd19 switching flag lcd18sel flg 15.69h.1 r/w p2a1/lcd18 switching flag lcd17sel flg 15.69h.0 r/w p2a0/lcd17 switching flag p0dpld3 flg 15.6ah.3 r/w pod3 pin pull-down resistor switching flag p0dpld2 flg 15.6ah.2 r/w pod2 pin pull-down resistor switching flag p0dpld1 flg 15.6ah.1 r/w pod1 pin pull-down resistor switching flag p0dpld0 flg 15.6ah.0 r/w pod0 pin pull-down resistor switching flag p2cbio3 flg 15.6bh.3 r/w p2c3 i/o select flag p2cbio2 flg 15.6bh.2 r/w p2c2 i/o select flag p2cbio1 flg 15.6bh.1 r/w p2c1 i/o select flag p2cbio0 flg 15.6bh.0 r/w p2c0 i/o select flag p2bbio3 flg 15.6ch.3 r/w p2b3 i/o select flag p2bbio2 flg 15.6ch.2 r/w p2b2 i/o select flag p2bbio1 flg 15.6ch.1 r/w p2b1 i/o select flag p2bbio0 flg 15.6ch.0 r/w p2b0 i/o select flag
238 m pd17933, 17934 symbol name attribute value r/w description p1dbio3 flg 15.6dh.3 r/w p1d3 i/o select flag p1dbio2 flg 15.6dh.2 r/w p1d2 i/o select flag p1dbio1 flg 15.6dh.1 r/w p1d1 i/o select flag p1dbio0 flg 15.6dh.0 r/w p1d0 i/o select flag p1abio3 flg 15.6eh.3 r/w p1a3 i/o select flag p1abio2 flg 15.6eh.2 r/w p1a2 i/o select flag p1abio1 flg 15.6eh.1 r/w p1a1 i/o select flag p1abio0 flg 15.6eh.0 r/w p1a0 i/o select flag p0bbio3 flg 15.6fh.3 r/w p0b3 i/o select flag p0bbio2 flg 15.6fh.2 r/w p0b2 i/o select flag p0bbio1 flg 15.6fh.1 r/w p0b1 i/o select flag p0bbio0 flg 15.6fh.0 r/w p0b0 i/o select flag 23.6 peripheral hardware register symbol name attribute value r/w description adcr dat 02h r/w a/d converter reference voltage set register sio1sfr dat 04h r/w serial interface 1 presettable shift register tm0m dat 1ah r/w timer modulo 0 register tm0c dat 1bh r timer modulo 0 counter ar dat 40h r/w address register dbfstk dat 41h r/w dbf stack register pllr dat 42h r/w pll data register ifc dat 43h r if counter data register 23.7 others symbol name attribute value description dbf dat 0fh operand (dbf) for get/put/movt/movth/movtl instruction ix dat 01h operand (ix) for inc instruction ar_epa1 dat 8040h operand (epa bit on) for call/br/movt/movth/movtl instruction ar_epa0 dat 4040h operand (epa bit off) for call/br/movt/movth/movtl instruction
239 m pd17933, 17934 24. electrical characteristics absolute maximum ratings (t a = 25 c) parameter symbol condition rating unit supply voltage v dd0 C0.3 to +2.0 v v dd1 C0.3 to +2.0 v v dd2 C0.3 to +2.0 v input voltage v i1 p0d0-p0d3, p1c0-p1c3 pins C0.3 to v dd2 +0.3 v v i2 vcoh and vcol pins C0.3 to v dd1 +0.3 v v i3 p0b0-p0b3, p1a0-p1a3, p1d0-p1d3, p2a0-p2a2, C0.3 to v dd0 +0.3 v p2b0-p2b3, p2c0-p2c3, reset, and int pins output voltage v o1 p0b0-p0b3, p0c0-p0c3, p2b0-p2b3, p2c0-p2c3 C0.3 to v dd0 +0.3 v v o2 eo1 and eo2 pins C0.3 to reg lcd 1+0.3 v v o3 lcd0-lcd19, com0-com3 pins C0.3 to reg lcd 2+0.3 v high-level output current i oh 1 pin C3.0 ma total of p0b0-p0b3, p0c0-p0c3, p2b0-p2b3, and C30.0 ma p2c0-p2c3 low-level output current i ol1 1 pin of p0a0, p0a1, and p1d0-p1d3 10.0 ma i ol2 1 pin other p0a0, p0a1, and p1d0-p1d3 3.0 ma total of p0a0, p0a1, p0b0-p0b3, p0c0-p0c3, 45.0 ma p1a0- p1a3, p1d0-p1d3, p2b0-p2b3, and p2c0-p2c3 output voltage v bds p0a0, p0a1, p1a0-p1a3, p1d0-p1d3 C0.3 to +4.0 v operating ambient t a C10 to +50 c temperature storage temperature t stg C55 to +125 c caution if the absolute maximum rating of even one of the above parameters is exceeded even momen- tarily, the quality of the product may be degraded. the absolute maximum ratings, therefore, specify the value exceeding which the product may be physically damaged. be sure to use the product with these ratings never being exceeded.
240 m pd17933, 17934 recommended supply voltage range (t a = C10 to +50 c) parameter symbol condition min. typ. max. unit supply voltage v dd0 1.05 1.8 v v dd1 1.05 1.8 v v dd2 1.05 1.8 v recommended output voltage (t a = C10 to +50 c) parameter symbol condition min. typ. max. unit output voltage v bds p0a0, p0a1, p1a0-p1a3, p1d0-p1d3 C0.3 +4.0 v
241 m pd17933, 17934 dc characteristics (t a = C10 to +50 c, v dd = v dd0 = v dd1 = v dd2 = 1.05 to 1.8 v) parameter symbol condition min. typ. max. unit supply current i dd11 cpu operation (v dd0 = 1.8 v, t a = 25 c) 120 320 m a i dd12 halt operation (v dd0 = 1.8 v, t a = 25 c) 70 240 m a i dd2 pll operation 7.0 10.0 ma (vcoh pin, f in = 130 mhz, v in = 0.5 v p-p , v dd = 1.8 v) i dd3 a/d converter, if counter operation 3.0 7.0 ma (f in = 10.7 mhz, v in = 0.3 v p-p , v dd2 = 1.8 v) high-level input voltage v ih1 p0b0-p0b3, p1a0-p1a3, p1c0-p1c3, p1d0-p1d3, 0.8 v dd v dd v p2a0-p2a2, p2b0-p2b3, p2c0-p2c3, reset, int v ih2 p0d0-p0d3 0.8 v dd v dd v low-level input voltage v il1 p0b0-p0b3, p1a0-p1a3, p1c0-p1c3, p1d0-p1d3, 0 0.1 v dd v p2a0-p2a2, p2b0-p2b3, p2c0-p2c3, reset, int v il2 p0d0-p0d3 0 0.1 v dd v high-level output voltage v oh1 p0b0-p0b3, p0c0-p0c3, p2b0-p2b3, p2c0-p2c3 v dd0 v v oh2 eo0, eo1 reg lcd 1 v v oh3 lcd0-lcd19, com0-com3 reg lcd 2 v high-level input current i ih1 with p0d0-p0d3 pulled down v ih = v dd0 = 1.1 v 2 30 m a v ih = v dd0 2 m a low-level input current i il1 with x in pin pulled up v ih = v dd0 = 1.1 v C2 C30 m a v ih = v dd0 C2 m a high-level output current i oh1 p0b0-p0b3, p0c0-p0c3, p2b0-p2b3, p2c0-p2c3 C0.13 ma (v oh = v dd1 C 0.2 v) i oh2 eo0, eo1 (v oh = v dd2 C 0.2 v) C0.13 ma i oh3 lcd0-lcd19 (v oh = lcd reg 2 C 0.2 v) C1 m a i oh4 com0-com3 (v oh = lcd reg 2 C 0.2 v) C10 m a low-level output current i ol1 p0b0-p0b3, p0c0-p0c3, p2b0-p2b3, p2c0-p2c3 0.2 ma (v ol = 0.2 v) i ol2 eo0, eo1 (v ol = 0.2 v) 0.2 ma i ol3 p1a0-p1a3 (v ol = 0.2 v) 0.4 ma i ol4 p0a0, p1a1, p1d0-p1d3 (v ol = 0.2 v) 6.0 ma i ol5 lcd0-lcd19 (v ol = 0.2 v) 1 m a i ol6 com0-com3 (v ol = 0.2 v) 10 m a lcd drive voltage v lcd0 lcd0-lcd19 output open, c1-c5 = 0.1 m f 1.4 1.5 1.6 v v lcd1 t a = 25 c 2.8 3.0 3.2 v output off leakage current i l1 p0a0, p0a1, p1a0-p1a3, p1d0-p1d3 (v oh = 1.8 v) 1 m a i l2 eo0, eo1 (v oh = 1.8 v, v ol = 0 v) 1 m a com intermediate v m com0-com3 (output open) v lcd0 v lcd0 v lcd0 v potential output voltage C0.2 +0.2 com intermediate i om com0-com3 (v om = v m 0.2 v) 1 m a potential output current remark unless otherwise specified, the characteristics of muxed pins are the same as those of the port pins.
242 m pd17933, 17934 ac characteristics (t a = C10 to +50 c, v dd = v dd0 = v dd1 = v dd2 = 1.05 to 1.8 v) parameter symbol condition min. typ. max. unit operating frequency f in1 vhf mode, sine wave input v in = 0.3 v p-p 35 220 mhz f in2 hf mode, sine wave input v in = 0.3 v p-p 5 40 mhz f in3 mf mode, sine wave input v in = 0.3 v p-p 0.8 3.5 mhz f in4 amifc pin, sine wave input v in = 0.3 v p-p 0.4 2 mhz f in5 amifc pin, sine wave input v in = 0.3 v p-p 0.4 2 mhz f in6 fmifc pin, sine wave input v in = 0.3 v p-p 10 11 mhz sck input frequency f in7 external clock 75 khz a/d converter characteristics (t a = C10 to +50 c, v dd = v dd0 = v dd1 = v dd2 = 1.05 to 1.8 v) parameter symbol condition min. typ. max. unit total conversion error v dd2 = 1.05 to 1.8 v 3 lsb
243 m pd17933, 17934 25. package drawing s80gk-50-9eu note each lead centerline is located within 0.10 mm (0.004 inch) of its true position (t.p.) at maximum material condition. item millimeters inches a b c d f g h i j k 14.0?.2 12.0?.2 1.25 0.22?.05 0.10 12.0?.2 l m 0.10 0.145?.05 1.0?.2 0.5 (t.p.) 0.5?.2 n 1.0?.05 14.0?.2 1.25 p 0.551?.008 0.472 0.551?.008 0.049 0.049 0.009 0.004 0.020 (t.p.) 0.039 0.020 0.006 0.004 0.040 +0.002 ?.003 0.472 +0.008 ?.009 q 0.1?.05 0.004?.002 s 1.2 max. 0.048 max. +0.002 ?.003 +0.009 ?.008 +0.009 ?.008 +0.009 ?.008 +0.002 ?.003 r3 3 +7 ? +7 ? 80 pin plastic tqfp (fine pitch) ( 12) b 60 a 41 40 21 61 80 120 c d g j h i m f n p k l m s r q detail of lead end
244 m pd17933, 17934 26. recommended soldering conditions solder the m pd17933 and m pd17934 under the following recommended conditions. for details of the recommended soldering conditions, refer to information document semiconductor device mounting technology manual (c10535e) . for soldering methods and conditions other than those recommended, consult nec. table 26-1. soldering conditions for surface-mount type m pd17933gk- -be9: 80-pin plastic tqfp (12 mm 12 mm, 0.5-mm pitch) m pd17934gk- -be9: 80-pin plastic tqfp (12 mm 12 mm, 0.5-mm pitch) soldering method soldering conditions recommended conditions symbol infrared reflow package peak temperature: 235 c; time: 30 secs. max. (210 c min.); ir35-107-2 number of times: twice max.; number of days: 7 note (after that, prebaking is necessary at 125 c for 10 hours) products other than in heat-resistance trays (such as those packaged in a magazine, taping, or non-heat-resistance tray) cannot be baked while they are in their package. vps package peak temperature: 215 c; time: 40 secs. max. (200 c min.); vp15-107-2 number of times: twice max.; number of days: 7 note (after that, prebaking is necessary at 125 c for 10 hours) products other than in heat-resistance trays (such as those packaged in a magazine, taping, or non-heat-resistance tray) cannot be baked while they are in their package. partial heating pin temperature: 300 c max.; time: 3 secs. max. (per device side) note number of days in storage after the dry pack has been opened. the storage conditions are at 25 c, 65 % rh max. caution do not use two or more soldering methods in combination (except partial heating).
245 m pd17933, 17934 appendix a. cautions on connecting crystal resonator when using the system clock oscillation circuit, wire the portion enclosed by the dotted line in the figure below as follows to prevent adverse influence from wiring capacity. ? keep the wiring length as short as possible. ? if capacitances c1 and c2 are too high, the oscillation start characteristics may be degraded or current consumption may increase. ? generally, connect a trimmer capacitor for adjusting the oscillation frequency to the x in pin. depending on the crystal resonator to be used, however, the oscillation stability differs. therefore, evaluate the crystal resonator actually used. ? the crystal oscillation frequency cannot be accurately adjusted when an emulation probe is connected to the x out and x in pin, because of the capacitance of the probe. adjust the frequency while measuring the vco oscillation frequency. pd17933 pd17934 75-khz crystal resonator c1 c2 x out x in m m
246 m pd17933, 17934 appendix b. development tools the following development tools are available for development of programs for the m pd17933 and 17934. hardware name outline ie-17k, ie-17k-et, and emu-17k are in-circuit emulators that can be used with any model in the 17k series. ie-17k and ie-17k-et are connected to a host machine, which is pc-9800 series or ibm pc/at tm , with rs-232c. emu-17k is mounted to the expansion slot of a host machine, pc-9800 series. by using these in-circuit emulators with a system evaluation board (se board) corresponding to each model, these emulators operate dedicated to the model. when man-machine interface software simplehost tm is used, a more sophisticated debugging environment can be created. emu-17k also has a function to allow you to check the contents of the data memory real-time. se-17934 is an se board for the m pd17933 and 17934. this board can be used alone to evaluate a system, or in combination with an in-circuit emulator for debugging. ep-17k80gk is an emulation probe for the m pd17933 and 17934. by using this probe with tgk- 080sdp note 3 , the se board and target system are connected. tgk-080sdp is a conversion socket for 80-pin plastic tqfp (12 12 mm). it is used to connect ep- 17k80gk and target system. notes 1. low-price model: external power supply type 2. this is a product of i.c corp. for details, consult i.c corp. (03-3447-3793). 3. a product of tokyo eletech corp. (03-5295-1661). consult your nec distributor when purchasing the product. remark third party prom programmers af-9703, af-9704, af-9705, and af-9706 are available from ando electric co., ltd. use these programmers with programmer adapter pa-17p709gc. for details, consult ando electric co., ltd. (03-3733-1163). in-circuit emulator ie-17k ie-17k-et note 1 emu-17k note 2 se board (se-17934) emulation probe (ep-17k80gk) conversion socket (tgk-080sdp note 3 )
247 m pd17933, 17934 software name outline host machine os parts number 17k series pc-9800 series ms-dos tm m s5a13ra17k assembler (ra17k) ibm pc/at pc dos tm m s7b13ra17k 17k series pc-9800 series ms-dos m s5a13cc17k c-like compiler ( emlc-17k tm ) ibm pc/at pc dos m s7b13cc17k device file pc-9800 series ms-dos m s5a13as17707 (as17934) ibm pc/at pc dos m s7b13as17707 support pc-9800 series ms-dos windows m s5a13ie17k software ( simplehost ) ibm pc/at pc dos m s7b13ie17k remark the version of the supported os is as follows: os version ms-dos ver.3.30 to ver.5.00a note pc dos ver.3.1 to ver.5.0 note windows ver.3.0 to ver.3.1 note ms-dos ver. 5.00/5.00a and pc dos ver. 5.0 have a task swap function, but this function cannot be used with this software. ra17k is a relocatable assembler that can be commonly used with 17k series. to develop programs for the m pd17933 and 17934, this ra17k and a device file (as17934) are used in combination. the ra17k is provided with linker (lk17k) and document processor (doc17k) utility. emlc-17k is a c-like compiler that can be used with all models on the 17k series. it is used together with ra17k. as17934 is a device file for the m pd17933 and 17934. it is used together with the assembler common to the 17k series (ra17k). simplehost is man-machine interface software that runs on windows tm when a program is developed by using an in-circuit emulator and personal computer.
248 m pd17933, 17934 [memo]
249 m pd17933, 17934 [memo]
250 m pd17933, 17934 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos device behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. produc- tion process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed imme- diately after power-on for devices having reset function.
251 m pd17933, 17934 nec electronics inc. (u.s.) santa clara, california tel: 408-588-6000 800-366-9782 fax: 408-588-6130 800-729-9288 nec electronics (germany) gmbh duesseldorf, germany tel: 0211-65 03 02 fax: 0211-65 03 490 nec electronics (uk) ltd. milton keynes, uk tel: 01908-691-133 fax: 01908-670-290 nec electronics italiana s.r.1. milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics singapore pte. ltd. united square, singapore 1130 tel: 65-253-8311 fax: 65-250-3583 nec electronics taiwan ltd. taipei, taiwan tel: 02-719-2377 fax: 02-719-5951 nec do brasil s.a. cumbica-guarulhos-sp, brasil tel: 011-6465-6810 fax: 011-6465-6829 nec electronics (germany) gmbh benelux office eindhoven, the netherlands tel: 040-2445845 fax: 040-2444580 nec electronics (france) s.a. velizy-villacoublay, france tel: 01-30-67 58 00 fax: 01-30-67 58 99 nec electronics (france) s.a. spain office madrid, spain tel: 01-504-2787 fax: 01-504-2860 nec electronics (germany) gmbh scandinavia office taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 regional information some information contained in this document may vary from country to country. before using any nec product in your application, please contact the nec office in your country to obtain a list of authorized representatives and distributors. they will verify: ? device availability ? ordering information ? product release schedule ? availability of related technical literature ? development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. j98. 2
no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. anti-radioactive design is not implemented in this product. m4 96.5 the export of this product from japan is regulated by the japanese government. to export this product may be prohibited without governmental license, the need for which must be judged by the customer. the export or re-export of this product from a country other than japan may also be prohibited without a license from that country. please call an nec sales representative. emlc-17k and simplehost are trademarks of nec corporation. ms-dos and windows are either registered trademarks or trademarks of microsoft corporation in the united states and/or other countries. pc/at and pc dos are trademarks of ibm corporation. m pd17933, 17934

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